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mixed signal isp flash mcu family c8051f54x rev. 1.1 4/11 copyright ? 2011 by silicon laboratories c8051f540/1/2/3/4/5/6/7 analog peripherals - 12-bit adc ? up to 200 ksps ? up to 25 external single-ended inputs ? vref from on-chip vref, external pin or v dd ? internal or external start of conversion source ? built-in temperature sensor - two comparators ? programmable hysteresis and response time ? configurable as interrupt or reset source ? low current on-chip debug - on-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) - provides breakpoints, single stepping, ? inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets - low cost, complete development kit supply voltage 1.8 to 5.25 v - typical operating current: 19 ma at 50 mhz; ? typical stop mode current: 1 a high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 50 mips throughput with 50 mhz clock - expanded interrupt handler memory - 1280 bytes internal data ram (256 + 1024 xram) - 16 or 8 kb flash; in-system programmable in ? 512-byte sectors digital peripherals - 25 or 18 port i/o; all 5 v tolerant - lin 2.1 controller (master and slave capable); no crystal required - hardware enhanced uart, smbus?, and enhanced spi? serial ports - four general purpose 16-bit counter/timers - 16-bit programmable coun ter array (pca) with six capture/compare modules and enhanced pwm functionality clock sources - internal 24 mhz with 0.5% accuracy master lin operation - external oscillator: crystal, rc, c, or clock ? (1 or 2 pin modes) - can switch between clo ck sources on-the-fly; ? useful in power saving modes packages - 32-pin qfp/qfn (c8051f540/1/4/5) - 24-pin qfn (c8051f542/3/6/7) automotive qualified - temperature range: ?40 to +125 c - compliant to aec-q100 analog peripherals 16 kb isp flash 1 kb xram por debug circuitry flexible interrupts 8051 cpu (50 mips) digital i/o 24 mhz precision internal oscillator high-speed controller core wdt 2x clock multiplier uart 0 smbus spi pca timers 0-3 crossbar lin ports 0-3 a m u x 12-bit 200 ksps adc temp sensor voltage comparators 0-1 vreg vref
c8051f54x 2 rev. 1.1
rev. 1.1 3 c8051f54x table of contents 1. system overview ........ ................ ................. ................ ................. ................ ........... 13 2. ordering information ....... ................ ................ ................. .............. .............. ........... 16 3. pin definitions........... ................ ................ ................. ................ ................. ............. 18 4. package specifications ... ................ ................ ................. .............. .............. ........... 23 4.1. qfp-32 package specifications ................ ................. .............. .............. ........... 23 4.2. qfn-32 package specifications ................ ................. .............. .............. ........... 25 4.3. qfn-24 package specifications ................ ................. .............. .............. ........... 27 5. 12-bit adc (adc0) ........ ................. ................ ................ ................. .............. ........... 29 5.1. modes of operation ... ................ ................ ................. .............. .............. ........... 30 5.2. output code formatting ....... ................. ................ ................. ................ ........... 34 5.3. selectable gain ...... ................. ................ ................ ................. .............. ........... 35 5.4. programmable window detector ............... ................. .............. .............. ........... 43 6. electrical characteristics ......... ................ ................. ................ ................. ............. 47 6.1. absolute maximum specificat ions................ .............. .............. .............. ........... 47 6.2. electrical characteri stics ................ .............. .............. .............. .............. ........... 48 6.1. adc0 analog multiplexer ..... ................. ................ ................. ................ ........... 58 6.2. temperature sensor.. ................ ................ ................. .............. .............. ........... 60 7. voltage reference....... ................ ................. ................ ................. ................ ........... 61 8. comparators.............. ................ ................ ................. ................ ................. ............. 63 8.1. comparator multiple xer ............... ................. .............. .............. .............. ........... 69 9. voltage regulator (reg0) ........ ................ ................. ................ ................. ............. 72 10. cip-51 microcontroller.............. ................. ................ ................. ................ ........... 74 10.1. performance ............ ................ ................ ................. .............. .............. ........... 74 10.2. instruction set....... ................. ................ ................ ................. .............. ........... 76 10.3. cip-51 register descriptions .. ................ ................. .............. .............. ........... 80 10.4. serial number special f unction registers (sfrs) ......... ............ ........... ......... 84 11. memory organization .... ................ ................ ................. .............. .............. ........... 85 11.1. program memory....... ................ ................. .............. .............. .............. ........... 85 11.2. data memory ........... ................ ................ ................. .............. .............. ........... 86 11.3. external ram .......... ................ ................ ................. .............. .............. ........... 87 12. special function registers...... ................. ................ ................. ................ ........... 89 12.1. sfr paging ............. ................ ................ ................. .............. .............. ........... 89 12.2. interrupts and sfr paging ...... ................ ................. .............. .............. ........... 89 12.3. sfr page stack exampl e ................ ................. ................ ................. ............. 91 13. interrupts ............ ................ ................. .............. .............. .............. .............. ......... 105 13.1. mcu interrupt sour ces and vectors........... .............. .............. .............. ......... 105 13.2. interrupt register descripti ons .............. ................ ................. .............. ......... 108 13.3. external interrupts int0 and int1 .............. .............. .............. .............. ..........115 14. flash memory.............. ................. ................ ................ ................. .............. ......... 117 14.1. programming the fl ash memory ................ .............. .............. .............. ......... 117 14.2. non-volatile data storage .. ................. ................ ................. ................ ......... 119 14.3. security options ...... ................ ................ ................. .............. .............. ......... 119 14.4. flash write and erase guidel ines .............. .............. .............. .............. ......... 121
c8051f54x 4 rev. 1.1 15. power management modes...... ................. ................ ................. ................ ......... 126 15.1. idle mode....... ................. .............. .............. .............. .............. .............. ......... 126 15.2. stop mode ............... ................ ................ ................. .............. .............. ......... 127 15.3. suspend mode .......... ................ ................. .............. .............. .............. ......... 127 16. reset sources ........... ................ ................. ................ ................. ................ ......... 129 16.1. power-on reset ...... ................ ................ ................. .............. .............. ......... 130 16.2. power-fail reset/vdd monito r .................. .............. .............. .............. ......... 130 16.3. external reset ................ .............. .............. .............. .............. .............. ......... 132 16.4. missing clock detector reset . ................ ................. .............. .............. ......... 132 16.5. comparator0 reset ............ ................. ................ ................. ................ ......... 133 16.6. pca watchdog timer reset ..... ................. .............. .............. .............. ......... 133 16.7. flash error reset .... ................ ................ ................. .............. .............. ......... 133 16.8. software reset ........ ................ ................ ................. .............. .............. ......... 133 17. oscillators and clock selection ............ ................. ................ ................. ........... 135 17.1. system clock selection...... ................. ................ ................. ................ ......... 135 17.2. programmable internal oscill ator ................... .............. ............... ........... ....... 137 17.3. clock multiplier ..... ................. ................ ................ ................. .............. ......... 140 17.4. external oscillator drive circuit........ ................. ................ ................. ........... 142 18. port input/output ...... ................ ................. ................ ................. ................ ......... 147 18.1. port i/o modes of operation. ................... ................. .............. .............. ......... 148 18.2. assigning port i/ o pins to analog and digital functi ons................. .............. 149 18.3. priority crossbar decoder .. ................. ................ ................. ................ ......... 150 18.4. port i/o initializatio n ................ ................ ................. .............. .............. ......... 152 18.5. port match ............ ................. ................ ................ ................. .............. ......... 157 18.6. special function regist ers for accessing an d configuring port i/o ............. 161 19. local interconnect network (l in)............. ................ ................. ................ ......... 170 19.1. software interface with the lin controller.................... ............... ........... ....... 171 19.2. lin interface setup and oper ation............. .............. .............. .............. ......... 171 19.3. lin master mode operation ... ............... ................ ................. .............. ......... 174 19.4. lin slave mode operation ...... ................ ................. .............. .............. ......... 175 19.5. sleep mode and wake-up ...... ................ ................. .............. .............. ......... 176 19.6. error detection and handling ... ............... ................. .............. .............. ......... 176 19.7. lin registers........... ................ ................ ................. .............. .............. ......... 177 20. smbus................. ................ ................. .............. .............. .............. .............. ......... 187 20.1. supporting document s ................. .............. .............. .............. .............. ......... 188 20.2. smbus configuration.......... ................. ................ ................. ................ ......... 188 20.3. smbus operation ...... ................ ................. .............. .............. .............. ......... 188 20.4. using the smbus..... ................ ................ ................. .............. .............. ......... 190 20.5. smbus transfer modes......... ................ ................ ................. .............. ......... 197 20.6. smbus status decodi ng................... ................. ................ ................. ........... 201 21. uart0 ................. ................ ................. .............. .............. .............. .............. ......... 205 21.1. baud rate generator ................ ................. .............. .............. .............. ......... 205 21.2. data format.......... ................. ................ ................ ................. .............. ......... 207 21.3. configuration and o peration ............... ................ ................. ................ ......... 208 22. enhanced serial peripheral in terface (spi0) ......... ................ ................. ........... 214
rev. 1.1 5 c8051f54x 22.1. signal descriptions.. ................ ................ ................. .............. .............. ......... 215 22.2. spi0 master mode op eration .............. ................ ................. ................ ......... 216 22.3. spi0 slave m ode operation .................. ................ ................. .............. ......... 218 22.4. spi0 interrupt sources ....... ................. ................ ................. ................ ......... 218 22.5. serial clock phase and polari ty .............. ................. .............. .............. ......... 219 22.6. spi special function register s .................. .............. .............. .............. ......... 220 23. timers ................... ................. ................ ................ ................. ................ .............. 22 7 23.1. timer 0 and timer 1 ... ............... ................. .............. .............. .............. ......... 229 23.2. timer 2 .......... ................. .............. .............. .............. .............. .............. ......... 237 23.3. timer 3 .......... ................. .............. .............. .............. .............. .............. ......... 243 24. programmable counter array............ .............. .............. .............. .............. ......... 249 24.1. pca counter/timer ............ ................. ................ ................. ................ ......... 250 24.2. pca0 interrupt sources...... ................. ................ ................. ................ ......... 251 24.3. capture/compare modules ..... ................ ................. .............. .............. ......... 252 24.4. watchdog timer mode ... .............. .............. .............. .............. .............. ......... 260 24.5. register descriptions for pc a0............. ................ ................. .............. ......... 263 25. c2 interface ............. ................ ................ ................. ................ ................. ........... 269 25.1. c2 interface registers........ ................. ................ ................. ................ ......... 269 25.2. c2 pin sharing ........ ................ ................ ................. .............. .............. ......... 272
c8051f54x 6 rev. 1.1 list of figures figure 1.1. c8051f540/1/ 4/5 block diagram ....... .............. .............. .............. ......... 14 figure 1.2. c8051f542/3/ 6/7 block diagram ....... .............. .............. .............. ......... 15 figure 3.1. qfp-32 pinout diagr am (top view) ........ ................ ................. ............. 20 figure 3.2. qfn-32 pinout diagr am (top view) ......... ................. ................ ........... 21 figure 3.3. qfn-24 pinout diagr am (top view) ......... ................. ................ ........... 22 figure 4.1. qfp-32 package drawin g ................ .............. .............. .............. ........... 23 figure 4.2. qfp-32 landi ng diagram ................ .............. .............. .............. ........... 24 figure 4.3. qfn-32 package drawin g ...................... ................ ................. ............. 25 figure 4.4. qfn-32 landi ng diagram ................ .............. .............. .............. ........... 26 figure 4.5. qfn-24 package drawin g ...................... ................ ................. ............. 27 figure 4.6. qfn-24 landi ng diagram ................ .............. .............. .............. ........... 28 figure 5.1. adc0 functional blo ck diagram ............. ................ ................. ............. 29 figure 5.2. adc0 tracking modes ................ ................ ................. .............. ........... 31 figure 5.3. 12-bit adc tracking mode example ......... ................. ................ ........... 32 figure 5.4. 12-bit adc burs t mode example with repeat c ount set to 4 ............. 33 figure 5.5. adc0 equivalent i nput circuit .............. .............. ............... ........... ......... 35 figure 5.6. adc window compar e example: right-justified da ta ............ ............. 46 figure 5.7. adc window compar e example: left-justified data .............. ............. 46 figure 6.1. minimum vdd m onitor threshold vs. system clock frequency ........... 50 figure 6.2. adc0 multiplexer bl ock diagram ............ ................ ................. ............. 58 figure 6.3. temperature sensor transfer function ............. ............... ........... ......... 60 figure 7.1. voltage reference functional block diagram ....... ............ ........... ......... 61 figure 8.1. comparator functi onal block diagram ..... ................. ................ ........... 63 figure 8.2. comparator hysteresis plot ................. .............. ............... ........... ......... 64 figure 8.3. comparator input multiplexer block diagram ..... ............... ........... ......... 69 figure 9.1. external capacitors for voltage regulator input/output? ? regulator enabled ......... ................. .............. .............. .............. .............. ........... 72 figure 9.2. external capacitors for vo ltage regulator input/o utput?regulator dis- abled ............. ................. .............. .............. .............. .............. .............. ........... 73 figure 10.1. cip-51 block diagram ............... ................ ................. .............. ........... 75 figure 11.1. c8051f54x memory m ap ...................... ................ ................. ............. 85 figure 11.2. flash program memo ry map .......... .............. .............. .............. ........... 86 figure 12.1. sfr page sta ck ................... ................. ................ ................. ............. 90 figure 12.2. sfr page sta ck while using sfr page 0x 0 to access smb0adr . 91 figure 12.3. sfr page stack afte r spi0 interrupt occurs ...... ............ ........... ......... 92 figure 12.4. sfr page stack upon pca interrupt occurrin g during a spi0 isr .. 93 figure 12.5. sfr page stack u pon return from pca interrupt ............... ............. 94 figure 12.6. sfr page stack u pon return from spi0 interrupt ............... ............. 95 figure 14.1. flash program memo ry map .......... .............. .............. .............. ......... 119 figure 16.1. reset sources ........ ................. ................ ................. ................ ......... 129 figure 16.2. power-on and v dd monitor reset timing ......... ............ ........... ....... 130 figure 17.1. oscillator options .. ............... ................. ................ ................. ........... 135 figure 17.2. example clock multip lier output ........... ................ ................. ........... 140
rev. 1.1 7 c8051f54x figure 17.3. external 32.768 khz quartz crystal oscillat or connection diagram 145 figure 18.1. port i/o f unctional block diagram ............... .............. .............. ......... 147 figure 18.2. port i/o ce ll block diagram ........ ................. .............. .............. ......... 148 figure 18.3. peripheral availabili ty on port i/o pins ............. ............... ........... ....... 151 figure 18.4. crossbar priority decoder in example configurat ion ............. ........... 152 figure 19.1. lin block diagram . ................. ................ ................. ................ ......... 170 figure 20.1. smbus block diagram ................ ................. .............. .............. ......... 187 figure 20.2. typical smbus confi guration ................ ................ ................. ........... 188 figure 20.3. smbus transaction ..... ................ ................. .............. .............. ......... 189 figure 20.4. typical smbus scl generation .............. ................. ................ ......... 191 figure 20.5. typical master wr ite sequence .............. ................. ................ ......... 198 figure 20.6. typical ma ster read sequence ....... .............. .............. .............. ....... 199 figure 20.7. typical sl ave write sequence .. ................ ................. .............. ......... 200 figure 20.8. typical slave read sequence ................ ................. ................ ......... 201 figure 21.1. uart0 block diagram ................ ................. .............. .............. ......... 205 figure 21.2. uart0 timing without parity or extra bit .... .............. .............. ......... 207 figure 21.3. uart0 timing with parity .......... ................. .............. .............. ......... 207 figure 21.4. uart0 timing with extra bit ............. .............. ............... ........... ....... 207 figure 21.5. typical uart inte rconnect diagram ................... ............ ........... ....... 208 figure 21.6. uart multi-proc essor mode interconne ct diagram ......... ................ 209 figure 22.1. spi block di agram ............... ................. ................ ................. ........... 214 figure 22.2. multiple-master mode connection diagram ........ ............ ........... ....... 217 figure 22.3. 3-wire single master and 3-wire single sl ave mode connection diagram 217 figure 22.4. 4-wire single master mode and 4-wire slave mode connection diagram 217 figure 22.5. master mode data/ clock timing ............. ................. ................ ......... 219 figure 22.6. slave mode data/clock timing (ckpha = 0) .. ............... ........... ....... 220 figure 22.7. slave mode data/clock timing (ckpha = 1) .. ............... ........... ....... 220 figure 22.8. spi master timing (ckpha = 0) .... .............. .............. .............. ......... 224 figure 22.9. spi master timing (ckpha = 1) .... .............. .............. .............. ......... 224 figure 22.10. spi slave timing (c kpha = 0) ............. ................. ................ ......... 225 figure 22.11. spi slave timing (c kpha = 1) ............. ................. ................ ......... 225 figure 23.1. t0 mode 0 bl ock diagram .............. .............. .............. .............. ......... 230 figure 23.2. t0 mode 2 bl ock diagram .............. .............. .............. .............. ......... 231 figure 23.3. t0 mode 3 bl ock diagram .............. .............. .............. .............. ......... 232 figure 23.4. timer 2 16-bit mode block diagram ....... ................. ................ ......... 237 figure 23.5. timer 2 8-bit mode block diagram ....... ................ ................. ........... 238 figure 23.6. timer 2 external oscillator capture mode blo ck diagram ..... ........... 239 figure 23.7. timer 3 16-bit mode block diagram ....... ................. ................ ......... 243 figure 23.8. timer 3 8-bit mode block diagram ....... ................ ................. ........... 244 figure 23.9. timer 3 external oscillator capture mode blo ck diagram ..... ........... 245 figure 24.1. pca block diagram ... ................ ................ ................. .............. ......... 249 figure 24.2. pca counter/timer block diagram ......... ................. ................ ......... 251
c8051f54x 8 rev. 1.1 figure 24.3. pca interrupt block diagram ................ ................ ................. ........... 252 figure 24.4. pca capture mode dia gram ............ .............. .............. .............. ....... 254 figure 24.5. pca software time r mode diagram ....... ................. ................ ......... 255 figure 24.6. pca high-speed out put mode diagram ... ................. .............. ......... 256 figure 24.7. pca frequen cy output mode .......... .............. .............. .............. ....... 257 figure 24.8. pca 8-bit pwm mode diagram ......... .............. ............... ........... ....... 258 figure 24.9. pca 9, 10 and 11-bi t pwm mode diagram .......... ................. ........... 259 figure 24.10. pca 16-bit pwm mode ................ .............. .............. .............. ......... 260 figure 24.11. pca module 2 wi th watchdog timer enabled .... ................. ........... 261 figure 25.1. typical c2 pin shar ing ................ ................. .............. .............. ......... 272
rev. 1.1 9 c8051f54x list of tables table 2.1. product select ion guide ................. ................. .............. .............. ........... 17 table 3.1. pin definitions for t he c8051f54x ............ ................ ................. ............. 18 table 4.1. qfp-32 package dimensions ........... .............. .............. .............. ........... 23 table 4.2. qfp-32 landing diagram dimensions .. .............. ............... ........... ......... 24 table 4.3. qfn-32 package dimensions ........... .............. .............. .............. ........... 25 table 4.4. qfn-32 landing diagram dimensions .. .............. ............... ........... ......... 26 table 4.5. qfn-24 package dimensions ........... .............. .............. .............. ........... 27 table 4.6. qfn-24 landing diagram dimensions .. .............. ............... ........... ......... 28 table 6.1. absolute maximum rati ngs ................... .............. ............... ........... ......... 47 table 6.2. global electrical char acteristics ............ .............. ............... ........... ......... 48 table 6.3. port i/ o dc electrical char acteristics ......... ................. ................ ........... 51 table 6.4. reset electric al characteristics ...... ................. .............. .............. ........... 52 table 6.5. flash electrical char acteristics ...... ................. .............. .............. ........... 52 table 6.6. internal high-frequency oscillator electrical char acteristics .... ............. 53 table 6.7. clock multiplier elec trical specifications ........... .............. .............. ......... 54 table 6.8. voltage regula tor electrical characteristics ..... .............. .............. ......... 54 table 6.9. adc0 elec trical characteristics .... ................ ................. .............. ........... 55 table 6.10. temperature sensor electrical char acteristics ............. .............. ......... 56 table 6.11. voltage reference elec trical characteristics ....... ............ ........... ......... 56 table 6.12. comparator 0 and comparator 1 electrical ch aracteristics . ................ 57 table 10.1. cip-51 instruction set summary ............ ................ ................. ............. 77 table 12.1. special function register (sfr) memory map for ? pages 0x0 and 0xf ....... ................ ................. .............. .............. ......... 100 table 12.2. special functi on registers .............. .............. .............. .............. ......... 101 table 13.1. interrupt summ ary ................. ................. ................ ................. ........... 107 table 14.1. flash security summar y ................. .............. .............. .............. ......... 120 table 18.1. port i/o a ssignment for analog functions ...... .............. .............. ....... 149 table 18.2. port i/o a ssignment for digital functions ...... .............. .............. ......... 149 table 18.3. port i/o assignmen t for external digital event capture functions .... 150 table 19.1. baud rate calculati on variable ranges .............. ............ ........... ....... 171 table 19.2. manual baud rate pa rameters examples ........... ............ ........... ....... 173 table 19.3. autobaud parameters ex amples .............. ................. ................ ......... 174 table 19.4. lin registers* (indire ctly addressable) .. ................ ................. ........... 179 table 20.1. smbus clock source selection .............. ................ ................. ........... 191 table 20.2. minimum sda setup and hold times ...... ................. ................ ......... 192 table 20.3. sources for hardwa re changes to smb0cn ......... ................. ........... 196 table 20.4. smbus status decoding ............... ................. .............. .............. ......... 202 table 21.1. baud rate genera tor settings for st andard baud rates ................... 206 table 22.1. spi slave timing para meters ......... .............. .............. .............. ......... 226 table 24.1. pca timebase input op tions ............ .............. .............. .............. ....... 250 table 24.2. pca0cpm and pc a0pwm bit settings for ? pca capture/compare modules .............. ................. ................ ......... 253 table 24.3. watchdog timer timeout intervals1 ......... ................. ................ ......... 262
c8051f54x 10 rev. 1.1 list of registers sfr definition 5.4. adc0cf: adc0 configuration ........ ................ ................. ............. 40 sfr definition 5.5. adc0h: adc0 data word msb ...... ................ ................. ............. 41 sfr definition 5.6. adc0l: adc0 data word lsb ............... .............. .............. ........... 41 sfr definition 5.7. adc0cn : adc0 control ........... .............. .............. .............. ........... 42 sfr definition 5.8. adc0tk: adc0 tracking mode select ......... ............ ........... ......... 43 sfr definition 5.9. adc0gth: adc0 greater-than da ta high byte ...... ........... ......... 44 sfr definition 5.10. adc0gtl: adc0 greater-than da ta low byte ...... ........... ......... 44 sfr definition 5.11. adc0lth: adc0 less-than data high byte ................. ............. 45 sfr definition 5.12. adc0ltl: ad c0 less-than data low byte ........... ........... ......... 45 sfr definition 6.3. adc0 mx: adc0 channel select ................ ............... ........... ......... 59 sfr definition 7.1. ref0cn : reference control .... .............. .............. .............. ........... 62 sfr definition 8.1. cpt0 cn: comparator0 control .............. .............. .............. ........... 65 sfr definition 8.2. cpt0 md: comparator0 mode selection .. .............. .............. ......... 66 sfr definition 8.3. cpt1 cn: comparator1 control .............. .............. .............. ........... 67 sfr definition 8.4. cpt1 md: comparator1 mode selection .. .............. .............. ......... 68 sfr definition 8.5. cpt0 mx: comparator0 mux sele ction ................. .............. ......... 70 sfr definition 8.6. cpt1 mx: comparator1 mux sele ction ................. .............. ......... 71 sfr definition 9.1. reg0cn : regulator control ..... .............. .............. .............. ........... 73 sfr definition 10.1. dpl: data po inter low byte ....... .............. ............... ........... ......... 81 sfr definition 10.2. dph: data pointer high byte .. .............. .............. .............. ........... 81 sfr definition 10.3. sp: st ack pointer ........ .............. .............. .............. .............. ......... 82 sfr definition 10.4. acc: accumulator ........ ................. ................ ................. ............. 82 sfr definition 10.5. b: b r egister ............. .............. .............. .............. .............. ........... 82 sfr definition 10.6. psw: program status word .......... ................ ................. ............. 83 sfr definition 10.7. snn: serial nu mber n ................. .............. ............... ........... ......... 84 sfr definition 11.1. emi0 cn: external memory interface co ntrol .............. ................ 88 sfr definition 12.1. sfr0cn: sfr page control ........... ................. ................ ........... 96 sfr definition 12.2. sfrpage: sfr page ............ .............. .............. .............. ........... 97 sfr definition 12.3. sfrnext: sfr ne xt ............. .............. .............. .............. ........... 98 sfr definition 12.4. sfrlast: sfr last ............ ................. .............. .............. ........... 99 sfr definition 13.1. ie: in terrupt enable .............. ................. .............. .............. ......... 109 sfr definition 13.2. ip: inte rrupt priority ............ ................ ................. .............. ......... 110 sfr definition 13.3. eie1 : extended interrupt enable 1 ......... .............. .............. ....... 111 sfr definition 13.4. eip1 : extended interrupt priority 1 ....... .............. .............. ......... 112 sfr definition 13.5. eie2 : extended interrupt enable 2 ......... .............. .............. ....... 113 sfr definition 13.6. eip2 : extended interrupt priority enabled 2 ................ .............. 114 sfr definition 13.7. it01cf: int0 /int1 configuration .. ................ ................. ........... 116 sfr definition 14.1. psctl: prog ram store r/w control ................ ................ ......... 122 sfr definition 14.2. flk ey: flash lock and key ..... .............. .............. .............. ....... 123 sfr definition 14.3. flscl: flash scale ............. ................. .............. .............. ......... 124 sfr definition 14.4. cch0cn : cache control ........ .............. .............. .............. ......... 125 sfr definition 14.5. oneshot: fl ash oneshot period .............. ............ ........... ....... 125 sfr definition 15.1. pcon: power control ............. .............. .............. .............. ......... 128
rev. 1.1 11 c8051f54x sfr definition 16.1. vdm0 cn: vdd monitor control ............. .............. .............. ....... 132 sfr definition 16.2. rstsrc : reset source ......... .............. .............. .............. ......... 134 sfr definition 17.1. clksel: clock select ............ .............. .............. .............. ......... 136 sfr definition 17.2. oscicn: inte rnal oscillator control ......... ............... ........... ....... 138 sfr definition 17.3. osci crs: internal oscillator coarse ca libration ........ .............. 139 sfr definition 17.4. oscifin: in ternal oscillator fine calibra tion .............. .............. 139 sfr definition 17.5. clkmul : clock multiplier ....... .............. .............. .............. ......... 141 sfr definition 17.6. oscx cn: external oscillator control ................. .............. ......... 143 sfr definition 18.1. xbr0: port i/o crossbar register 0 ..... .............. .............. ......... 154 sfr definition 18.2. xbr1: port i/o crossbar register 1 ..... .............. .............. ......... 155 sfr definition 18.3. xbr2: port i/o crossbar register 1 ..... .............. .............. ......... 156 sfr definition 18.4. p0mask: port 0 mask register ..... ................ ................. ........... 157 sfr definition 18.5. p0mat: port 0 match register ... .............. ............... ........... ....... 157 sfr definition 18.6. p1mask: port 1 mask register ..... ................ ................. ........... 158 sfr definition 18.7. p1mat: port 1 match register ... .............. ............... ........... ....... 158 sfr definition 18.8. p2mask: port 2 mask register ..... ................ ................. ........... 159 sfr definition 18.9. p2mat: port 2 match register ... .............. ............... ........... ....... 159 sfr definition 18.10. p3ma sk: port 3 mask register ................. ............ ........... ....... 160 sfr definition 18.11. p3mat: port 3 match register .... ................ ................. ........... 160 sfr definition 18.12. p0: port 0 .... ................ ................. ................ ................. ........... 161 sfr definition 18.13. p0mdin: port 0 input mode ......... ................ ................. ........... 162 sfr definition 18.14. p0md out: port 0 output mode ........... .............. .............. ....... 162 sfr definition 18.15. p0skip: port 0 skip ........... ................. .............. .............. ......... 163 sfr definition 18.16. p1: port 1 .... ................ ................. ................ ................. ........... 163 sfr definition 18.17. p1mdin: port 1 input mode ......... ................ ................. ........... 164 sfr definition 18.18. p1md out: port 1 output mode ........... .............. .............. ....... 164 sfr definition 18.19. p1skip: port 1 skip ........... ................. .............. .............. ......... 165 sfr definition 18.20. p2: port 2 .... ................ ................. ................ ................. ........... 165 sfr definition 18.21. p2mdin: port 2 input mode ......... ................ ................. ........... 166 sfr definition 18.22. p2md out: port 2 output mode ........... .............. .............. ....... 166 sfr definition 18.23. p2skip: port 2 skip ........... ................. .............. .............. ......... 167 sfr definition 18.24. p3: port 3 .... ................ ................. ................ ................. ........... 167 sfr definition 18.25. p3mdin: port 3 input mode ......... ................ ................. ........... 168 sfr definition 18.26. p3md out: port 3 output mode ........... .............. .............. ....... 168 sfr definition 18.27. p3skip: port 3skip ............ ................. .............. .............. ......... 169 sfr definition 19.1. lin0 adr: lin0 indirect a ddress register .......... .............. ......... 177 sfr definition 19.2. lin0da t: lin0 indirect data register .. .............. .............. ......... 177 sfr definition 19.3. lin0cf: lin0 control mode register ............... ................ ......... 178 sfr definition 20.1. smb0cf: smbu s clock/configuration ........ ............ ........... ....... 193 sfr definition 20.2. smb0cn: smbu s control .............. ................ ................. ........... 195 sfr definition 20.3. smb0dat: smbu s data ................ ................ ................. ........... 197 sfr definition 21.1. scon0: serial port 0 control ..... .............. ............... ........... ....... 210 sfr definition 21.2. smod0: serial port 0 control ................... ............... ........... ....... 211 sfr definition 21.3. sbuf0: seri al (uart0) port data buffer . ............... ........... ....... 212 sfr definition 21.4. sbcon0: ua rt0 baud rate generator cont rol ........... ........... 212
c8051f54x 12 rev. 1.1 sfr definition 21.6. sbrll0: uart0 baud rate generator re load low byte ........ 213 sfr definition 21.5. sbrlh0: uart0 baud rate generator reload high byte ....... 213 sfr definition 22.1. spi0cfg: spi 0 configuration ....... ................ ................. ........... 221 sfr definition 22.2. spi0cn : spi0 control ............ .............. .............. .............. ......... 222 sfr definition 22.3. spi0ckr: spi 0 clock rate ........... ................ ................. ........... 223 sfr definition 22.4. spi0dat: spi0 data ........... ................. .............. .............. ......... 223 sfr definition 23.1. ckcon: clock control ........... .............. .............. .............. ......... 228 sfr definition 23.2. tcon: timer c ontrol .............. .............. .............. .............. ......... 233 sfr definition 23.3. tmod: timer m ode ................ .............. .............. .............. ......... 234 sfr definition 23.4. tl0: timer 0 low byte ......... ................. .............. .............. ......... 235 sfr definition 23.5. tl1: timer 1 low byte ......... ................. .............. .............. ......... 235 sfr definition 23.6. th0: timer 0 high byte .............. .............. ............... ........... ....... 236 sfr definition 23.7. th1: timer 1 high byte .............. .............. ............... ........... ....... 236 sfr definition 23.8. tmr2cn: timer 2 control ............. ................ ................. ........... 240 sfr definition 23.9. tmr2rll: ti mer 2 reload register low byte ............... ........... 241 sfr definition 23.10. tmr2 rlh: timer 2 reload register high byte . .............. ....... 241 sfr definition 23.11. tmr2l: timer 2 low byte .... .............. .............. .............. ......... 242 sfr definition 23.12. tmr2h timer 2 high byte ........... ................ ................. ........... 242 sfr definition 23.13. tmr3 cn: timer 3 control .... .............. .............. .............. ......... 246 sfr definition 23.14. tmr3 rll: timer 3 reload re gister low byte ... .............. ....... 247 sfr definition 23.15. tmr3 rlh: timer 3 reload register high byte . .............. ....... 247 sfr definition 23.16. tmr3l: timer 3 low byte .... .............. .............. .............. ......... 248 sfr definition 23.17. tmr3h timer 3 high byte ........... ................ ................. ........... 248 sfr definition 24.1. pca0cn : pca control ........... .............. .............. .............. ......... 263 sfr definition 24.2. pca0md: pca mo de ............. .............. .............. .............. ......... 264 sfr definition 24.3. pca0pwm: pca pwm configuration ......... ............ ........... ....... 265 sfr definition 24.4. pca0cpmn : pca capture/compare mode .. ................. ........... 266 sfr definition 24.5. pca 0l: pca counter/timer low byte ................. .............. ....... 267 sfr definition 24.6. pca0h: pca counter/timer high byte ....... ............ ........... ....... 267 sfr definition 24.7. pca0cpln: pca capture module low byte . ................. ........... 268 sfr definition 24.8. pca0cphn: pca capture module high byte ................ ........... 268
rev. 1.1 13 c8051f54x 1. system overview c8051f54x devices are fully integr ated mixed-signal system-on-a-ch ip mcus. highlighted features are listed below. refer to table 2.1 for specific pr oduct feature selection and part ordering numbers. ? high-speed pipelined 8051-compatible microcontroller core (up to 50 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? lin 2.1 peripheral (fully backwards compatib le, master and slave modes) (c8051f540/2/4/6) ? true 12-bit 200 ksps 32-channel single-ended adc with analog multiplexer ? precision programmable 24 mhz internal oscillator that is wit hin 0.5% across the temperature range and for vdd voltages greater than or equal to the on-chip voltage regulator minimum output at the low setting. the oscillator is within + 1.0% for vdd voltages below th is minimum output setting. ? on-chip clock multiplier to reach up to 50 mhz ? 16 kb (c8051f540/1/2/3) or 8 kb (c8051f544/5/6/7) of on-chip flash memory ? 1280 bytes of on-chip ram ? smbus/i2c, enhanced uart, and enhanced spi serial interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with six capture/compare modules and watchdog timer function ? on-chip voltage regulator ? on-chip power-on reset, v dd monitor, and temperature sensor ? on-chip voltage comparator ? 25 or 18 port i/o (5 v push-pull) with on-chip voltage regulator, power-on reset, v dd monitor, watchdog timer, and clock oscillator, the c8051f54x devices are truly stand-alone system-on- a-chip solutions. the flash memory can be repro- grammed even in-circuit, providing non-volatile data st orage, and also allowing field upgrades of the 8051 firmware. user software has complete control of all pe ripherals, and may individually shut down any or all peripherals for power savings. the on-chip silicon labs 2- wire (c2) development interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions, allowing in-system debugging with- out occupying package pins. the devices are specified for 1.8 v to 5.25 v operat ion over the automotive te mperature range (?40 to +125 c). the c8051f540/1/4/5 devices are ava ilable in 32-pin qfp and qfn packages and the c8051f542/3/6/7 devices are available in 32-pin qf n packages. all package options are lead-free and rohs compliant. see table 2.1 for ordering information. block diagrams are included in figure 1.1 and figure 1.2.
c8051f54x 14 rev. 1.1 figure 1.1. c8051f540/1/4/5 block diagram digital peripherals uart0 timers 0, 1, 2, 3 6 channel pca/wdt lin 2.1 priority crossbar decoder p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 crossbar control port i/o configuration sfr bus p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 i2c debug / programming hardware power on reset reset c2ck/rst p1.6 p1.7 analog peripherals comparator 0 + - 12-bit 200ksps adc a m u x vref vdd vdd vref gnd cp0, cp0a voltage reference vref system clock setup external oscillator xtal1 cip-51 8051 controller core (50 mhz) 16 kb flash program memory 256 byte ram port 0 drivers port 1 drivers voltage regulator (ldo) gnd vregin vdd xtal2 vio p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 port 2 drivers temp sensor p0 ? p3 gnda vdda clock multiplier internal oscillator (0.5%) 1 kb xram spi comparator 1 + - cp1, cp1a p3.0/c2d port 3 driver c2d
rev. 1.1 15 c8051f54x figure 1.2. c8051f542/3/6/7 block diagram digital peripherals uart0 timers 0, 1, 2, 3 6 channel pca/wdt lin 2.1 priority crossbar decoder p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 crossbar control port i/o configuration sfr bus p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 i2c debug / programming hardware power on reset reset c2ck/rst p1.6 p1.7 analog peripherals comparator 0 + - 12-bit 200ksps adc a m u x vref vdd vdd vref gnd cp0, cp0a voltage reference vref system clock setup external oscillator xtal1 cip-51 8051 controller core (50 mhz) 16 kb flash program memory 256 byte ram port 0 drivers port 1 drivers voltage regulator (ldo) gnd vregin vdd xtal2 vio p2.0 p2.1/c2d port 2 drivers temp sensor p0 ? p2 gnda clock multiplier internal oscillator (0.5%) 1 kb xram spi comparator 1 + - cp1, cp1a c2d
c8051f54x 16 rev. 1.1 2. ordering information the following features are common to all devices in this family: ? 50 mhz system clock and 50 mips throughput (peak) ? 1280 bytes of ram (256 internal bytes and 1024 xram bytes) ? internal 24 mhz oscillator ? smbus / i2c, enhanced spi, enhanced uart ? four timers ? six programmable counter array channels ? internal voltage regulator ? 12-bit, 200 ksps adc, internal voltage reference and temperature sensor ? two analog comparators ? table 2.1 shows the features that diff erentiate the devices in this family.
rev. 1.1 17 c8051f54x note: the suffix of the part number indicates the device rating and the package. all devices are rohs compliant. all of these devices are also available in an automotiv e version. for the automotive version, the -i in the ordering part number is replaced with -a. for example, the automotive version of the C8051F540-IM is the c8051f540-am. the -am and -aq devices receive full automotive qua lity production status, including aec-q100 qualifica- tion, registration with internationa l material data system (imds) and part production approval process (ppap) documentation. ppap docume ntation is available at www.silabs.com with a registered and nda approved user account. the -am and -aq devices enable high volume automot ive oem applications with their enhanced testing and processing. please contact silicon labs sales for mo re information regarding ? ?am and -aq devices for your automotive project. table 2.1. product selection guide ordering part number flash memory (kb) lin2.1 digital port i/os package c8051f540-iq 16 ? 25 qfp32 C8051F540-IM 16 ? 25 qfn32 c8051f541-iq 16 ? 25 qfp32 c8051f541-im 16 ? 25 qfn32 c8051f542-im 16 ? 18 qfn24 c8051f543-im 16 ? 18 qfn24 c8051f544-iq 8 ? 25 qfp32 c8051f544-im 8 ? 25 qfn32 c8051f545-iq 8 ? 25 qfp32 c8051f545-im 8 ? 25 qfn32 c8051f546-im 8 ? 18 qfn24 c8051f547-im 8 ? 18 qfn24
c8051f54x 18 rev. 1.1 3. pin definitions table 3.1. pin definitions for the c8051f54x name pin ?f540/1/4/5 (32-pin) pin ?f542/3/6/7 (24-pin) type description vdd 4 3 digital supply voltage. must be connected. gnd 6 4 digital ground. must be connected. vdda 5 ? analog supply voltage. must be connected. connected internally to vdd on the 24-pin packages. gnda 7 5 analog ground. must be connected. vregin 3 2 voltage regulator input vio 2 1 port i/o supply voltage. must be connected. rst / c2ck 10 8 d i/o d i/o device reset. open-drain output of internal por or v dd monitor. clock signal for the c2 debug interface. p2.1/ c2d ? 7 d i/o or a in d i/o port 2.1. see sfr definition 18.20 for a description. bi-directional data signal for the c2 debug interface. p3.0/ c2d 9 ? d i/o or a in d i/o port 3.0. see sfr definition 18.24 for a description. bi-directional data signal for the c2 debug interface. p0.0 8 6 d i/o or a in port 0.0. see sfr definition 18.12 for a description. p0.1 1 24 d i/o or a in port 0.1 p0.2 32 23 d i/o or a in port 0.2 p0.3 31 22 d i/o or a in port 0.3 p0.4 30 21 d i/o or a in port 0.4 p0.5 29 20 d i/o or a in port 0.5 p0.6 28 19 d i/o or a in port 0.6 p0.7 27 18 d i/o or a in port 0.7 p1.0 26 17 d i/o or a in port 1.0. see sfr definition 18.16 for a description. p1.1 25 16 d i/o or a in port 1.1. p1.2 24 15 d i/o or a in port 1.2.
rev. 1.1 19 c8051f54x p1.3 23 14 d i/o or a in port 1.3. p1.4 22 13 d i/o or a in port 1.4. p1.5 21 12 d i/o or a in port 1.5. p1.6 20 11 d i/o or a in port 1.6. p1.7 19 10 d i/o or a in port 1.7. p2.0 18 9 d i/o or a in port 2.0. see sfr definition 18.20 for a description. p2.1 17 ? d i/o or a in port 2.1. p2.2 16 ? d i/o or a in port 2.2. p2.3 15 ? d i/o or a in port 2.3. p2.4 14 ? d i/o or a in port 2.4. p2.5 13 ? d i/o or a in port 2.5. p2.6 12 ? d i/o or a in port 2.6. p2.7 11 ? d i/o or a in port 2.7. table 3.1. pin definitions for the c8051f54x (continued) name pin ?f540/1/4/5 (32-pin) pin ?f542/3/6/7 (24-pin) type description
c8051f54x 20 rev. 1.1 figure 3.1. qfp-32 pinout diagram (top view) 1 vregin p1.2 p1.7 p1.4 p1.3 p1.5 gnda vio p2.0 p2.1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p1.6 c8051f540-iq c8051f541-iq c8051f544-iq c8051f545-iq top view p0.0 / vref vdd vdda p0.1 / cnvstr p2.6 p2.5 p2.4 p2.3 p2.2 p1.1 p1.0 p2.7 p0.6 / can tx p0.5 / uart0 rx p0.4 / uart0 tx rst / c2ck p3.0 / c2d gnd p0.7 / can rx p0.3 / xtal2 p0.2 / xtal1
rev. 1.1 21 c8051f54x figure 3.2. qfn-32 pinout diagram (top view) p2.0 p1.7 p1.6 p1.5 p1.4 p1.3 21 22 23 19 18 20 p1.2 24 p2.1 17 gnd vio vregin vdd vdda gnd gnda 5 6 7 4 3 2 p0.0 / vref 8 p0.1 / cnvstr 1 p1.0 p0.7 / can rx p0.6 / can tx p0.5 / uart0 rx p0.4 / uart0 tx p0.3 / xtal2 29 30 31 27 26 28 p0.2 / xtal1 32 p1.1 25 C8051F540-IM c8051f541-im c8051f544-im c8051f545-im top view rst / c2ck p2.7 p2.6 p2.5 p2.4 p2.3 13 14 15 11 10 12 p2.2 16 p3.0 / c2d 9
c8051f54x 22 rev. 1.1 figure 3.3. qfn-24 pinout diagram (top view) gnd p1.4 p1.3 p1.2 p1.1 p1.0 p0.7/can0 rx 15 14 13 17 18 16 p2.1/c2d rst/c2ck p2.0 p1.7 p1.6 p1.5 10 11 12 8 7 9 vio vregin vdd gnd gnda p0.0/vref 4 5 6 2 1 3 p0.6/can0 tx p0.5/uart0 rx p0.4/uart0 tx p0.3/xtal2 p0.2/xtal1 p0.1/cnvstr 22 23 24 20 19 21 c8051f542-im c8051f543-im c8051f546-im c8051f547-im top view
rev. 1.1 23 c8051f54x 4. package specifications 4.1. qfp-32 package specifications figure 4.1. qfp-32 package drawing table 4.1. qfp-32 package dimensions dimension min typ max dimension min typ max a ? ? 1.60 e 9.00 bsc. a1 0.05 ? 0.15 e1 7.00 bsc. a2 1.35 1.40 1.45 l 0.45 0.60 0.75 b 0.30 0.37 0.45 aaa 0.20 c 0.09 ? 0.20 bbb 0.20 d 9.00 bsc. ccc 0.10 d1 7.00 bsc. ddd 0.20 e 0.80 bsc. ? 0 3.5 7 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec outline ms-0 26, variation bba. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components.
c8051f54x 24 rev. 1.1 figure 4.2. qfp-32 landing diagram table 4.2. qfp-32 landing diagram dimensions dimension min max dimension min max c1 8.40 8.50 x1 0.40 0.50 c2 8.40 8.50 y1 1.25 1.35 e 0.80 bsc notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. card assembly 7. a no-clean, type-3 solder paste is recommended. 8. recommended card reflow profile is per the jede c/ipc j-std-020 specification for small body components.
rev. 1.1 25 c8051f54x 4.2. qfn-32 package specifications figure 4.3. qfn-32 package drawing table 4.3. qfn-32 package dimensions dimension min typ max dimension min typ max a 0.80 0.9 1.00 e2 3.20 3.30 3.40 a1 0.00 0.02 0.05 l 0.30 0.40 0.50 b 0.18 0.25 0.30 l1 0.00 ? 0.15 d 5.00 bsc. aaa ? ? 0.15 d2 3.20 3.30 3.40 bbb ? ? 0.15 e 0.50 bsc. ddd ? ? 0.05 e 5.00 bsc. eee ? ? 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhd except for custom features d2, e2, and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components.
c8051f54x 26 rev. 1.1 figure 4.4. qfn-32 landing diagram table 4.4. qfn-32 landing diagram dimensions dimension min max dimension min max c1 4.80 4.90 x2 3.20 3.40 c2 4.80 4.90 y1 0.75 0.85 e 0.50 bsc y2 3.20 3.40 x1 0.20 0.30 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 3x3 array of 1.0 mm openings on a 1.20 mm pitc h should be used for the center ground pad. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specif ication for small body components.
rev. 1.1 27 c8051f54x 4.3. qfn-24 package specifications figure 4.5. qfn-24 package drawing table 4.5. qfn-24 package dimensions dimension min typ max dimension min typ max a 0.70 0.75 0.80 l 0.30 0.40 0.50 a1 0.00 0.02 0.05 l1 0.00 0.15 b 0.18 0.25 0.30 aaa 0.15 d 4.00 bsc bbb 0.10 d2 2.55 2.70 2.80 ddd 0.05 e 0.50 bsc eee 0.08 e 4.00 bsc z 0.24 e2 2.55 2.70 2.80 y 0.18 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec solid state outline mo-220, variation wggd, except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components.
c8051f54x 28 rev. 1.1 figure 4.6. qfn-24 landing diagram table 4.6. qfn-24 landing diagram dimensions dimension min max dimension min max c1 3.90 4.00 x2 2.70 2.80 c2 3.90 4.00 y1 0.65 0.75 e 0.50 bsc y2 2.70 2.80 x1 0.20 0.30 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished sten cil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center ground pad. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specif ication for small body components. ?
rev. 1.1 29 c8051f54x 5. 12-bit adc (adc0) the adc0 on the c8051f54x consists of an analog mu ltiplexer (amux0) with 25/1 8 total input selections and a 200 ksps, 12-bit successive -approximation-register (sar) adc with integrated track-and-hold, pro- grammable window detector, programmable attenuation (1:2), and hardware accumulator. the adc0 sub- system has a special burst mode which can auto matically enable adc0, capture and accumulate samples, then place adc0 in a low power shutdow n mode without cpu intervention. the amux0, data conversion modes, and window detector are all configur able under software control via the special func- tion registers shows in figure 5.1. adc0 inputs are single-ended and may be configured to measure p0.0-p3.7, the temperature sensor output, v dd , or gnd with respect to gnd. the voltage reference for adc0 is selected as described in section ?6.2. temperature sensor? on page 60. adc0 is enabled when the ad0en bit in the adc0 control register (adc0cn) is set to logic 1, or when performing conversions in burst mode. adc0 is in low power shutdown when ad0en is logic 0 and no burst mode conversions are taking place. figure 5.1. adc0 functional block diagram adc0cn ad0cm0 ad0cm1 ad0ljst ad0wint ad0busy ad0int bursten ad0en start conversion vdd 28-to-1 amux0 vdd p0.0 p0.7 p1.0 p1.7 adc0mx adc0mx4 adc0mx3 adc0mx2 adc0mx1 adc0mx0 gnd temp sensor adc0tk ad0pwr3 ad0pwr2 ad0pwr1 ad0pwr0 ad0tm1 ad0tm0 ad0tk1 ad0tk0 burst mode logic start conversion burst mode oscillator 25 mhz max sysclk fclk p2.2-p2.7, p3.0 available on 32-pin packages 00 ad0busy (w) 10 cnvstr input timer 2 overflow 11 01 timer 1 overflow 12-bit sar adc ref fclk adc0h 32 adc0lth ad0wint adc0ltl adc0gth adc0gtl adc0l adc0cf gainen ad0rpt0 ad0rpt1 ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 ad0post ad0pre ad0tm1:0 accumulator window compare logic selectable gain p2.0 p2.7 p3.0 adc0gnl adc0gnh adc0gna
c8051f54x 30 rev. 1.1 5.1. modes of operation in a typical system, adc0 is co nfigured using the following steps: 1. if a gain adjustment is required, refer to section ?5.3. selectable gain? on page 35. 2. choose the start of conversion source. 3. choose normal mode or burst mode operation. 4. if burst mode, choose the adc0 idle power state and set the power-up time. 5. choose the tracking mode. note that pre-tracking mode can only be used with normal mode. 6. calculate the required settling time and set the post convert-start tracking time using the ad0tk bits. 7. choose the repeat count. 8. choose the output word justificati on (right-justified or left-justified). 9. enable or disable the end of conversion and window comparator interrupts. 5.1.1. starting a conversion a conversion can be initiated in one of four ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm1 ? 0) in register adc0cn. conversions may be initiated by one of the fol- lowing: ? writing a 1 to the ad0busy bit of register adc0cn ? a rising edge on the cnvstr input signal (pin p0.1) ? a timer 1 overflow (i.e., timed continuous conversions) ? a timer 2 overflow (i.e., timed continuous conversions) ? writing a 1 to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand.? during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt flag (ad0int). note: when polling for adc conversion completions, the adc0 in terrupt flag (ad0int) should be used. converted data is available in th e adc0 data registers, adc0h:adc0l, when bit ad0int is logic 1. note that when timer 2 overflows are us ed as the conversion source, low byte overflows are used if timer2 is in 8-bit mode; high byte overflows are used if timer 2 is in 16-bit mode. see section ?23. timers? on page 227 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as port pin p0.1. when the cnvstr input is used as the adc0 conversion source, port pin p0.1 should be skipped by the digital crossbar. to configure the crossbar to skip p0.1, set to 1 bit1 in register p0ski p. see section ?18. port input/output? on page 147 for deta ils on port i/o configuration. 5.1.2. tracking modes each adc0 conversion must be prec eded by a minimum tracking time for the converted result to be accu- rate. adc0 has three tracking modes: pre-tracking, post-tracking, and dual-tracking. pre-tracking mode provides the minimum delay between the convert start signal and end of conversion by tracking continu- ously before the convert start signal. this mode requ ires software management in order to meet minimum tracking requirements. in post-tracking mode, a progra mmable tracking time starts after the convert start signal and is managed by hardware. dual-tracking mode maximizes tracking time by tracking before and after the convert start signal. figure 5.2 sh ows examples of the three tracking modes. pre-tracking mode is selected when ad0tm is set to 10b. conversions are started immediately following the convert start signal. adc0 is tracking continu ously when not performing a conversion. software must allow at least the minimum tracking time between each end of conversion and the next convert start signal. the minimum tracking time must also be met prior to the first convert start signal after adc0 is enabled.
rev. 1.1 31 c8051f54x post-tracking mode is selected w hen ad0tm is set to 01b. a programmable tracking time based on ad0tk is started immediately following the convert start signal. conversions are started after the pro- grammed tracking time ends. after a conversion is complete, adc0 does not track the input. rather, the sampling capacitor remains disconnected from the in put making the input pin high-impedance until the next convert start signal. dual-tracking mode is selected w hen ad0tm is set to 11b. a programmable tracking time based on ad0tk is started immediately following the convert start signal. conversions are started after the pro- grammed tracking time ends. after a conversion is complete, adc0 trac ks continuously until the next con- version is started. depending on the output connected to the adc input, additional tracking time, more than is specified in table 6.9, may be required after changing mux settings. see the settling time requirements described in section ?5.2.1. settling time requirements? on page 34. figure 5.2. adc0 tracking modes 5.1.3. timing adc0 has a maximum conversion speed specified in t able 6.9. adc0 is clocked from the adc0 subsys- tem clock (fclk). the source of fclk is selected based on the bursten bit. when bursten is logic 0, fclk is derived from the current system cl ock. when bursten is logic 1, fclk is derived from the burst mode oscillator, an in dependent clock source with a ma ximum frequency of 25 mhz. when adc0 is performing a conversion, it requires a clock source that is typically slower than fclk. the adc0 sar conversion clock (sar clock) is a divided version of fclk. the divide ratio can be configured using the ad0sc bits in the adc0cf register. the maximum sar clock frequency is listed in table 6.9. adc0 can be in one of three states at any given time : tracking, converting, or idle. tracking time depends on the tracking mode selected. for pre-tracking mode, tracking is managed by software and adc0 starts conversions immediately following the convert start signal. for post-tracking and dual-tracking modes, the tracking time after the convert start signal is equal to the value determined by the ad0tk bits plus 2 fclk cycles. tracking is immediately followed by a conversion. the adc0 conversion time is always 13 sar clock cycles plus an additional 2 fclk cycles to start and complete a conversion. figure 5.3 shows timing diagrams for a conversion in pre-tracking mo de and tracking plus conversion in post-tracking or dual-tracking mode. in this example, repeat count is set to one. convert start post-tracking ad0tm= 01 track convert idle idle track convert.. pre-tracking ad0tm = 10 track convert track convert ... dual-tracking ad0tm = 11 track convert track track track convert..
c8051f54x 32 rev. 1.1 figure 5.3. 12-bit adc tracking mode example 5.1.4. burst mode burst mode is a power saving feature that allows adc0 to remain in a very low power state between con- versions. when burst mode is enabled, adc0 wakes from a very low power state, accumulates 1, 4, 8, or 16 samples using an internal burst mode clock (approximately 25 mhz), then re-enters a very low power state. since the burst mode clock is independent of th e system clock, adc0 can perform multiple conver- sions then enter a very low power state within a single syst em clock cycle, even if the system clock is slow (e.g., 32.768 khz) , or suspended. burst mode is enabled by setting bursten to logic 1. when in burst mode, ad0en controls the adc0 idle power state (i.e. the state adc0 enters when not tr acking or performing conversions). if ad0en is set to logic 0, adc0 is powered down after each burst. if ad0en is set to logic 1, adc0 remains enabled after each burst. on each convert start signal, adc0 is awak ened from its idle power state. if adc0 is powered down, it will automatically power up and wait th e programmable po wer-up time controlled by the ad0pwr bits. otherwise, adc0 will start tracking an d converting immediately. figure 5.4 shows an exam- ple of burst mode operation with a slow system clock and a repeat count of 4. important note: when burst mode is enabled, only post-tracking and dual-tracking modes can be used. when burst mode is enabled, a single convert start will initiate a numb er of conversions e qual to th e repeat count. when burst mode is disabled, a convert start is required to initiate each conversion. in both modes, the adc0 end of conversion interrupt flag (ad0int) will be set after ?repea t count? conversions have convert start adc0 state track adc0 state convert time f s1 s2 s12 s13 ... f time f s1 s2 s12 s13 ... f convert f s1 s2 f post-tracking or dual-tracki ng modes (ad0tk = ?00') pre-tracking mode ad0int flag ad0int flag key f s n equal to one period of fclk. each sn is equal to one period of the sar clock.
rev. 1.1 33 c8051f54x been accumulated. similarl y, the window comparator will not compare the result to the greater-than and less-than registers until ?repeat count? conversions have been accumulated. note: when using burst mode, care must be taken to iss ue a convert start signal no faster than once every four sysclk periods. this includes external convert start signals. figure 5.4. 12-bit adc burst mode example with repeat count set to 4 track.. system clock convert start (ad0busy or timer overflow) post-tracking ad0tm = 01 ad0en = 0 powered down powered down t c power-up and idle t c t c t c power-up and idle t c.. dual-tracking ad0tm = 11 ad0en = 0 powered down powered down t c power-up and track t c t c t c power-up and track t c.. ad0pwr post-tracking ad0tm = 01 ad0en = 1 idle idle t c t c t c t c t c.. dual-tracking ad0tm = 11 ad0en = 1 track track t c t c t c t c t c.. t c t c t c t c t = tracking c = converting convert start (cnvstr) post-tracking ad0tm = 01 ad0en = 0 powered down powered down t c power-up and idle power-up and idle t c.. dual-tracking ad0tm = 11 ad0en = 0 powered down powered down t c power-up and track power-up and track t c.. ad0pwr post-tracking ad0tm = 01 ad0en = 1 idle idle t c dual-tracking ad0tm = 11 ad0en = 1 track track t c t c t c t = tracking c = converting idle..
c8051f54x 34 rev. 1.1 5.2. output code formatting the registers adc0h and adc0l contain the high and lo w bytes of the output conversion code. when the repeat count is set to 1, conversion codes are represen ted in 12-bit unsigned integer format and the output conversion code is updated after each conv ersion. inputs are measured from 0 to v ref x 4095/4096. data can be right-justified or left-justified, depending on the setting of the ad0ljst bit (adc0cn.2). unused bits in the adc0h and adc0l registers are set to 0. example codes are shown below for both right-justi- fied and left-justified data. when the adc0 repeat count is greater than 1, the output conversion code represents the accumulated result of the conversions pe rformed and is updated after the last conv ersion in the series is finished. sets of 4, 8, or 16 consecutive samples can be accumulated and represented in unsigned integer format. the repeat count can be selected using the ad0rpt bits in the adc0cf register. the value must be right-jus- tified (ad0ljst = 0), and unused bits in the adc0h and adc0l registers are set to 0. the following example shows right-justified codes for repeat count s greater than 1. notice that accumulating 2 n samples is equivalent to left-shifting by n bit positions when all samples returned from the adc have the same value. 5.2.1. settling time requirements a minimum tracking time is required before an accura te conversion is performe d. this tracking time is determined by any series impedance, including th e amux0 resistance, the adc0 sampling capacitance, and the accuracy required for the conversion. figure 5.5 shows the equivalent adc0 input circuit. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 5.1. when measuring the temperature sensor output, use the settling time specified in table 6.10. when measuring v dd with respect to gnd, r total reduces to r mux . see table 6.9 for adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. equation 5.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb). t is the required sett ling time in seconds. r total is the sum of the amux0 resistance and any external source resistance. n is the adc resolution in bits (10). input voltage right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 4095/4096 0x0fff 0xfff0 vref x 2048/4096 0x0800 0x8000 vref x 2047/4096 0x07ff 0x7ff0 0 0x0000 0x0000 input voltage repeat count = 4 repeat count = 8 repeat count = 16 v ref x 4095/4096 0x3ffc 0x7ff8 0xfff0 v ref x 2048/4096 0x2000 0x4000 0x8000 v ref x 2047/4096 0x1ffc 0x3ff8 0x7ff0 0 0x0000 0x0000 0x0000 t 2 n sa ------- - ?? ?? r total c sample ? ln =
rev. 1.1 35 c8051f54x figure 5.5. adc0 equivalent input circuit 5.3. selectable gain adc0 on the c8051f54x family of devices implements a selectable gain adjustment option. by writing a value to the gain adjust address range, the user can select gain values between 0 and 1.016. for example, three analog sources to be measured ha ve full-scale outputs of 5.0 v, 4.0 v, and 3.0 v, respectively. each adc measurement would ideally use the full dynamic range of the adc with an internal voltage reference of 1.5 v or 2.2 v (set to 2.2 v for this example). when selecting the first source (5.0 v full-scale), a gain value of 0.44 (5 v full scale x 0.44 = 2.2 v full scale) provides a full-scale signal of 2.2 v when the input signal is 5.0 v. likewise, a gain value of 0.55 (4 v full scale x 0.55 = 2.2 v full scale) for the second source and 0.73 (3 v full scale x 0.73 = 2.2 v full scale) for the third sour ce provide full-scale adc0 measurements when the input signal is full-scale. additionally, some sensors or other input sources ha ve small part-to-part variations that must be accounted for to achieve accurate results. in this case, the programmable gain value could be used as a calibration value to eliminate these part-to-part variations. 5.3.1. calculating the gain value the adc0 selectable gain feature is controlled by 13 bits in three registers. adc0gnh contains the 8 upper bits of the gain value and adc0gnl contains th e 4 lower bits of the gain value. the final gainadd bit (adc0gna.0) controls an optional extra 1/64 (0.0 16) of gain that can be added in addition to the adc0gnh and adc0gnl gain. the adc0gna.0 bit is set to 1 after a power-on reset. the equivalent gain for the adc0gnh, adc0 gnl and adc0gna registers is as follows: equation 5.2. equivalent gain from the adc0gnh and adc0gnl registers where: gain is the 12-bit word of ad c0gnh[7:0] and adc0gnl[7:4] gainadd is the value of the gainadd bit (adc0gna.0) gain is the equivalent gain value from 0 to 1.016 r mux = tbd c sample = tbd rc in p u t = r mux * c sample mux select px.x gain gain 4096 --------------- ?? ?? gainadd 1 64 ----- - ?? ?? ? + =
c8051f54x 36 rev. 1.1 for example, if adc0gnh = 0xfc, adc0gnl = 0x00, and gainadd = 1, gain = 0xfc0 = 4032, and the resulting equation is as follows: the table below equates values in the adc0gnh, ad c0gnl, and adc0gna registers to the equivalent gain using this equation. for any desired gain value, the gain regi sters can be calculated by the following: equation 5.3. calculating the adc0gnh and adc0gnl values from the desired gain where: gain is the 12-bit word of ad c0gnh[7:0] and adc0gnl[7:4] gainadd is the value of the gainadd bit (adc0gna.0) gain is the equivalent gain value from 0 to 1.016 when calculating the value of gain to load into the adc0gnh and adc0gnl re gisters, the gainadd bit can be turned on or off to reach a value closer to the desired gain value. for example, the initial example in th is section requires a gain of 0.44 to convert 5 v full scale to 2.2 v full scale. using equation 5.3: if gainadd is set to 1, this makes the equation: the actual gain from setting gainadd to 1 and ad c0gnh and adc0gnl to 0x6ca is 0.4399. a similar gain can be achieved if gainadd is set to 0 with a different value for adc0gnh and adc0gnl. adc0gnh value adc0gnl value gainadd value gain value equivalent gain 0xfc (default) 0x00 (default) 1 (default) 4032 + 64 1.0 (default) 0x7c 0x00 1 1984 + 64 0.5 0xbc 0x00 1 3008 + 64 0.75 0x3c 0x00 1 960 + 64 0.25 0xff 0xf0 0 4095 + 0 ~1.0 0xff 0xf0 1 4096 + 64 1.016 gain 4032 4096 ------------ - ?? ?? 1 1 64 ------ ?? ?? ? + 0.984 0.016 +1.0 === gain gain gainadd 1 64 ----- - ?? ?? ? ? ?? ?? 4096 ? = gain 0.44 gainadd 1 64 ----- - ?? ?? ? ? ?? ?? 4096 ? = gain 0.44 1 1 64 ----- - ?? ?? ? ? ?? ?? 4096 ? 0.424 4096 ? 1738 0 x 06 ca ====
rev. 1.1 37 c8051f54x 5.3.2. setting the gain value the three programmable gain registers are accessed indirectly using the ad c0h and adc0l registers when the gainen bit (adc0cf.0) bit is set. adc0h ac ts as the address register, and adc0l is the data register. the programmable gain registers can only be written to and cannot be read. see gain register definition 5.1, gain register definition 5.2, and gain register definition 5.3 for more information. the gain is programmed using the following steps: 1. set the gainen bit (adc0cf.0) 2. load the adc0h with the adc0g nh, adc0gnl, or adc0gna address. 3. load adc0l with the desired value for the selected gain register. 4. reset the gainen bit (adc0cf.0) ? notes: 1. an adc conversion should not be performed while the gainen bit is set . 2. even with gain enabled, the maximum input voltage must be less than v regin and the maximum voltage of the signal after gain must be less than or equal to v ref . in code, changing the value to 0.44 gain from the previous example looks like: // in ?c?: adc0cf |= 0x01; // gainen = 1 adc0h = 0x04; // load the adc0gnh address adc0l = 0x6c; // load the upper byte of 0x6ca to adc0gnh adc0h = 0x07; // load the adc0gnl address adc0l = 0xa0; // load the lower nibble of 0x6ca to adc0gnl adc0h = 0x08; // load the adc0gna address adc0l = 0x01; // set the gainadd bit adc0cf &= ~0x01; // gainen = 0 ; in assembly orl adc0cf,#01h ; gainen = 1 mov adc0h,#04h ; load the adc0gnh address mov adc0l,#06ch ; load the upper byte of 0x6ca to adc0gnh mov adc0h,#07h ; load the adc0gnl address mov adc0l,#0a0h ; load the lower nibble of 0x6ca to adc0gnl mov adc0h,#08h ; load the adc0gna address mov adc0l,#01h ; set the gainadd bit anl adc0cf,#0feh ; gainen = 0
c8051f54x 38 rev. 1.1 indirect address = 0x04; indirect address = 0x07; gain register definition 5.1. adc0gnh: adc0 sel ectable gain high byte bit 7 6 5 4 3 2 1 0 name gainh[7:0] type w reset 1 1 1 1 1 1 0 0 bit name function 7:0 gainh[7:0] adc0 gain high byte. see section 5.3.1 for details on calculating the value for this register. note: this register is accessed indirectly; see section 5.3.2 for details for writing this register. gain register definiti on 5.2. adc0gnl: adc0 selectable gain low byte bit 7 6 5 4 3 2 1 0 name gainl[3:0] reserved reserved reserved reserved type w w w w w reset 0 0 0 0 0 0 0 0 bit name function 7:4 gainl[3:0] adc0 gain lower 4 bits. see figure 5.3.1 for details for setting this register. this register is only accessed indirect ly through the adc0h and adc0l register. 3:0 reserved must write 0000b note: this register is accessed indirectly; see section 5.3.2 for details for writing this register.
rev. 1.1 39 c8051f54x indirect address = 0x08; gain register definition 5.3. adc0gna: adc0 a dditional selectable gain bit 7 6 5 4 3 2 1 0 name reserved reserved reserved reserved reserved reserved reserved gainadd type w w w w w w w w reset 0 0 0 0 0 0 0 1 bit name function 7:1 reserved must write 0000000b. 0 gainadd adc0 additional gain bit. setting this bit add 1/64 (0.016) gain to the gain value in the adc0gnh and adc0gnl registers. note: this register is accessed indirectly; see section 5.3.2 for details for writing this register.
c8051f54x 40 rev. 1.1 sfr address = 0xbc; sfr page = 0x00 sfr definition 5.4. adc0cf: adc0 configuration bit 7 6 5 4 3 2 1 0 name ad0sc[4:0] ad0rpt[1:0] gainen type r/w r/w r/w r/w reset 1 1 1 1 1 0 0 0 bit name function 7:3 ad0sc[4:0] adc0 sar conversion cl ock period bits. sar conversion clock is derived from syste m clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4 ? 0. sar conversion clock requirements are given in the adc specification table bursten = 0: fclk is the current system clock bursten = 1: fclk is a maximum of 30 mhz, independent of the current system clock.. note: round up the result of the calculation for ad0sc 2:1 a0rpt[1:0] adc0 repeat count controls the number of conversions taken and accumulated between adc0 end of conversion (adcint) and adc0 window comparator (adcwint) interrupts. a con - vert start is required for each conversion unless burst mode is enabled. in burst mode, a single convert start can initiate mu ltiple self-timed conversions. results in both modes are accumulated in the adc0h:adc0l register. when ad0rpt1?0 are set to a value other than '00', the ad0ljst bit in the adc0cn register must be set to '0' (right justified). 00: 1 conversion is performed. 01: 4 conversions are performed and accumulated. 10: 8 conversions are performed and accumulated. 11: 16 conversions are performed and accumulated. 0 gainen gain enable bit. controls the gain programming. refer to section ?5.3. selectable gain? on page 35 for information about using this bit. ad0sc fclk clk sar -------------------- 1 ? =
rev. 1.1 41 c8051f54x sfr address = 0xbe; sfr page = 0x00 sfr address = 0xbd; sfr page = 0x00 sfr definition 5.5. adc0h: adc0 data word msb bit 7 6 5 4 3 2 1 0 name adc0h[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 adc0h[7:0] adc0 data word high-order bits. for ad0ljst = 0 and ad0rpt as follows: 00: bits 3?0 are the upper 4 bits of the 12-bit result. bits 7?4 are 0000b. 01: bits 4?0 are the upper 5 bits of the 14-bit result. bits 7?5 are 000b. 10: bits 5?0 are the upper 6 bits of the 15-bit result. bits 7?6 are 00b. 11: bits 7?0 are the upper 8 bits of the 16-bit result. for ad0ljst = 1 (ad0rpt must be 00): bits 7?0 are the most-significant bits of the adc0 12-bit result. sfr definition 5.6. adc0l: adc0 data word lsb bit 7 6 5 4 3 2 1 0 name adc0l[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 adc0l[7:0] adc0 data word low-order bits. for ad0ljst = 0: bits 7?0 are the lower 8 bits of the adc0 accumulated result. for ad0ljst = 1 (ad0rpt must be '00'): bits 7 ? 4 are the lower 4 bits of the 12-bit result. bits 3 ? 0 are 0000b.
c8051f54x 42 rev. 1.1 sfr address = 0xe8; sfr page = 0x00; bit-addressable sfr definition 5.7. adc0cn: adc0 control bit 7 6 5 4 3 2 1 0 name ad0en bursten ad0int ad0busy ad0wint ad0ljst ad0cm[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ad0en adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. 6 bursten adc0 burst mode enable bit. 0: burst mode disabled. 1: burst mode enabled. 5 ad0int adc0 conversion comple te interrupt flag. 0: adc0 has not completed a data conv ersion since ad0int was last cleared. 1: adc0 has completed a data conversion. 4 ad0busy adc0 busy bit. read: 0: adc0 conversion is not in progress. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conver - sion if ad0cm[1 : 0] = 00b 3 ad0wint adc0 window compare interrupt flag. this bit must be cleared by software 0: adc0 window comparison data match ha s not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. 2 ad0ljst adc0 left justify select bit. 0: data in adc0h:adc0l re gisters is right-justified 1: data in adc0h:adc0 l registers is left-justified. this option should not be used with a repeat count greater than 1 (when ad0rpt[1:0] is 01b, 10b, or 11b). 1:0 ad0cm[1:0] adc0 start of conversion mode select. 00: adc0 start-of-conversion sour ce is write of 1 to ad0busy. 01: adc0 start-of-conversion source is overflow of timer 1. 10: adc0 start-of-conversion source is rising edge of external cnvstr. 11: adc0 start-of-conversion source is overflow of timer 2.
rev. 1.1 43 c8051f54x sfr address = 0xba; sfr page = 0x00; 5.4. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro- grammed limits, and notifies the system when a desired co ndition is detected. this is especially effective in an interrupt-driven system, saving code space and cpu ba ndwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison valu es. the window detector flag can be programmed to indicate when mea- sured data is inside or outside of the user-progr ammed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr definition 5.8. adc0tk: adc0 tr acking mode select bit 7 6 5 4 3 2 1 0 name ad0pwr[3:0] ad0tm[1:0] ad0tk[1:0] type r/w r/w r/w reset 1 1 1 1 1 1 1 1 bit name function 7:4 ad0pwr[3:0] adc0 burst power-up time. for bursten = 0: adc0 power state controlled by ad0en for bursten = 1, ad0en = 1: adc0 re mains enabled and does not enter the very low power state for bursten = 1, ad0en = 0: adc0 ente rs the very low power state and is enabled after each convert start signal. the power-up time is programmed accord - ing the following equation: or 3:2 ad0tm[1:0] adc0 tracking mode enable select bits. 00: reserved. 01: adc0 is configured to post-tracking mode. 10: adc0 is configured to pre-tracking mode. 11: adc0 is configured to dual tracking mode. 1:0 ad0tk[1:0] adc0 post-track time. 00: post-tracking time is equal to 2 sar clock cycles + 2 fclk cycles. 01: post-tracking time is equal to 4 sar clock cycles + 2 fclk cycles. 10: post-tracking time is equal to 8 sar clock cycles + 2 fclk cycles. 11: post-tracking time is equal to 16 sar clock cycles + 2 fclk cycles. ad0pwr tstartup 200ns ------------- ----------- 1 ? = tstartup ad0pwr 1 + ?? 200ns =
c8051f54x 44 rev. 1.1 sfr address = 0xc4; sfr page = 0x00 sfr address = 0xc3; sfr page = 0x00 sfr definition 5.9. adc0gth: adc0 greater -than data high byte bit 7 6 5 4 3 2 1 0 name adc0gth[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 adc0gth[7:0] adc0 greater-than data word high-order bits. sfr definition 5.10. adc0gtl: adc0 greater- than data low byte bit 7 6 5 4 3 2 1 0 name adc0gtl[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 adc0gtl[7:0] adc0 greater-than data word low-order bits.
rev. 1.1 45 c8051f54x sfr address = 0xc6; sfr page = 0x00 sfr address = 0xc5; sfr page = 0x00 5.4.1. window detector in single-ended mode figure 5.6 shows two example window co mparisons for right-justified data with adc0lth:adc0ltl = 0x0200 (512d) and adc0gth:adc0gtl = 0x0100 (256d). the input voltage can range from 0 to v ref x (4095/4096) with respect to gnd, and is represented by a 12-bit unsigned integer value. the repeat count is set to one. in the left exampl e, an ad0wint interrupt will be generated if the adc0 conversion word (adc0h: adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0100 < adc0h:adc0l < 0x0200) . in the right example, and ad0wint interrupt will be generated if the adc0 conversion word is outside of the range defi ned by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0100 or adc0h:adc0l > 0x0200). figure 5.7 shows an exam- ple using left-justified data with the same comparison values. sfr definition 5.11. adc0lth: adc0 less-than data high byte bit 7 6 5 4 3 2 1 0 name adc0lth[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 adc0lth[7:0] adc0 less-than data word high-order bits. sfr definition 5.12. adc0ltl: adc0 less-than data low byte bit 7 6 5 4 3 2 1 0 name adc0ltl[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 adc0ltl[7:0] adc0 less-than data word low-order bits.
c8051f54x 46 rev. 1.1 figure 5.6. adc window compare example: right-justified data figure 5.7. adc window compare example: left-justified data 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 0 input voltage (px.x - gnd) vref x (4095/4096) vref x (512/4096) vref x (256/4096) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 0 input voltage (px.x - gnd) vref x (1023/ 1024) vref x (512/4096) vref x (256/4096) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 0 input voltage (px.x - gnd) vref x (4095/4096) vref x (512/4096) vref x (256/4096) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 0 input voltage (px.x - gnd) vref x (4095/4096) vref x (512/4096) vref x (256/4096) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl
rev. 1.1 47 c8051f54x 6. electrical characteristics 6.1. absolute m aximum specifications table 6.1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 135 c storage temperature ?65 ? 150 c voltage on v regin with respect to gnd ?0.3 ? 5.5 v voltage on v dd with respect to gnd ?0.3 ? 2.8 v voltage on vdda with respect to gnd ?0.3 ? 2.8 v voltage on v io with respect to gnd ?0.3 ? 5.5 v voltage on any port i/o pin or rst with respect to gnd ?0.3 ? v io + 0.3 v maximum total current through v regin or gnd ? ? 500 ma maximum output current sunk by rst or any port pin ? ? 100 ma maximum output current sourced by any port pin ? ? 100 ma note: stresses outside of the range of the ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the devices at thos e or any other conditions outside of those indicated in the oper ation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
c8051f54x 48 rev. 1.1 6.2. electrical characteristics table 6.2. global electrical characteristics ?40 to +125 c, 24 mhz system clock unless otherwise specified. parameter conditions min typ max units supply input voltage (v regin ) 1.8 ? 5.25 v digital supply voltage (v dd ) system clock < 25 mhz system clock > 25 mhz v rst 1 ?2.75 v 2 ? 2.75 analog supply voltage (vdda) (must be connected to v dd ) system clock < 25 mhz system clock > 25 mhz v rst 1 ?2.75 v 22.75 port i/o supply voltage (v io ) normal operation 1.8 2 ?5.25 v digital supply ram data retention voltage ?1.5? v sysclk (system clock) 3 0?50mhz t sysh (sysclk high time) 9 ? ? ns t sysl (sysclk low time) 9 ? ? ns specified operating temperature range ?40 ? +125 c digital supply current?cpu active (normal mode, fetching instructions from flash) i dd 4 v dd = 2.1 v, f = 200 khz ? 85 ? a v dd = 2.1 v, f = 1.5 mhz ? 600 ? a v dd = 2.1 v, f = 25 mhz ? 9.2 11 ma v dd = 2.1 v, f = 50 mhz ? 17 21 ma i dd 4 v dd = 2.6 v, f = 200 khz ? 120 ? a v dd = 2.6 v, f = 1.5 mhz ? 920 ? a v dd = 2.6 v, f = 25 mhz ? 13 21 ma v dd = 2.6 v, f = 50 mhz ? 22 33 ma i dd supply sensitivity 4 f = 25 mhz ? 68 ? %/v f = 1 mhz ? 77 ? %/v i dd frequency sensitivity 4,5 v dd = 2.1 v, f < 12.5 mhz, t = 25 c ? 0.43 ? ma/mhz v dd = 2.1 v, f > 12.5 mhz, t = 25 c ? 0.33 ? ma/mhz v dd = 2.6 v, f < 12.5 mhz, t = 25 c ? 0.60 ? ma/mhz v dd = 2.6 v, f > 12.5 mhz, t = 25 c ? 0.42 ? ma/mhz notes: 1. given in table 6.4 on page 52 . 2. v io should not be lower than the v dd voltage. 3. sysclk must be at least 32 khz to enable debugging. 4. guaranteed by characterization. does not include oscillator supply current. 5. idd estimation for different frequencies. 6. idle idd estimation for different frequencies.
rev. 1.1 49 c8051f54x digital supply current?cpu inactive (idle mode , not fetching instructions from flash) i dd 4 v dd = 2.1 v, f = 200 khz ? 50 ? a v dd = 2.1 v, f = 1.5 mhz ? 410 ? a v dd = 2.1 v, f = 25 mhz ? 6.5 8.0 ma v dd = 2.1 v, f = 50 mhz ? 13 16 ma i dd 4 v dd = 2.6 v, f = 200 khz ? 67 ? a v dd = 2.6 v, f = 1.5 mhz ? 530 ? a v dd = 2.6 v, f = 25 mhz ? 8.0 15 ma v dd = 2.6 v, f = 50 mhz ? 16 25 ma i dd supply sensitivity 4 f = 25 mhz ? 55 ? %/v f = 1 mhz ? 58 ? i dd frequency sensitivity 4.6 v dd = 2.1v, f < 12.5 mhz, t = 25 c ? 0.26 ? ma/mhz v dd = 2.1v, f > 12.5 mhz, t = 25 c ? 0.26 ? v dd = 2.6v, f < 12.5 mhz, t = 25 c ? 0.34 ? v dd = 2.6v, f > 12.5 mhz, t = 25 c ? 0.34 ? digital supply current 4 ? (stop or suspend mode) oscillator not running, v dd monitor disabled a te m p = 2 5 c?1? te m p = 6 0 c?6? temp= 125 c?70? table 6.2. global electrical characteristics (continued) ?40 to +125 c, 24 mhz system cl ock unless otherwise specified. parameter conditions min typ max units notes: 1. given in table 6.4 on page 52. 2. v io should not be lower than the v dd voltage. 3. sysclk must be at least 32 khz to enable debugging. 4. guaranteed by characterization. does not include oscillator supply current. 5. idd estimation for different frequencies. 6. idle idd estimation for different frequencies.
c8051f54x 50 rev. 1.1 figure 6.1. minimum vdd monitor threshold vs. system clock frequency note: with system clock frequencies greater than 25 mhz, the v dd monitor level should be set to the high threshold (vdmlvl = 1b in sfr vdm0cn) to prevent undefined cp u operation. the high threshold should only be used with an external regulator powering v dd directly. see figure 9.2 on page 73 for the recommended power supply connections.
rev. 1.1 51 c8051f54x table 6.3. port i/o dc electrical characteristics v dd = 1.8 to 2.75 v, ?40 to +125 c unless otherwise specified. parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull v io ? 0.4 v io ? 0.02 ? ? ? v io ? 0.7 ? ? ? v output low voltage v io = 1.8 v: i ol = 70 a i ol = 8.5 ma v io = 2.7 v: i ol = 70 a i ol = 8.5 ma v io = 5.25 v: i ol = 70 a i ol = 8.5 ma ? ? ? ? ? ? ? ? ? ? ? ? 50 750 45 550 40 400 mv input high voltage v regin = 5.25 v 0.7 x vio ? v input low voltage v regin = 2.7 v ? ? 0.3 x vio v input leakage ? current weak pullup off weak pullup on, v io = 2.1 v, ? v in = 0 v, v dd = 1.8 v weak pullup on, v io = 2.6 v, ? v in = 0 v, v dd = 2.6 v weak pullup on, v io = 5.0 v, ? v in = 0 v, v dd = 2.6 v ? ? ? ? ? 7 17 49 2 9 22 115 a
c8051f54x 52 rev. 1.1 table 6.4. reset electrical characteristics ?40 to +125 c unless otherwise specified. parameter conditions min typ max units rst output low voltage vio = 5 v; iol = 70 a ? ? 40 mv rst input high voltage 0.7 x v io ? ? rst input low voltage ? ? 0.3 x v io rst input pullup current rst = 0.0 v, vio = 5 v ? 49 115 a v dd rst threshold (v rst-low ) 1.65 1.75 1.80 v v dd rst threshold (v rst-high ) 2.25 2.30 2.45 v missing clock detector timeout time from last system clock rising edge to reset initiation v dd = 2.1 v v dd = 2.5 v 200 200 340 250 600 600 s reset time delay delay between release of any reset source and code ? execution at location 0x0000 ? 155 175 s minimum rst low time to ? generate a system reset 6 ? ? s v dd monitor turn-on time ? 60 100 s v dd monitor supply current ? 1 2 a table 6.5. flash electrical characteristics v dd = 1.8 to 2.75 v, ?40 to +125 c unless otherwise specified. parameter conditions min typ max units flash size c8051f540/1/2/3 16384 1 bytes c8051f544/5/6/7 8192 endurance 20 k 150 k ? erase/write retention 125 c 10 ? ? years erase cycle time 25 mhz system clock 28 30 45 ms write cycle time 25 mhz system clock 79 84 125 s v dd write/erase operations v rst-high 2 ? ? v 1. on the 16 kb flash devices, 1024 bytes at addresses 0x3c00 to 0x3fff are reserved. 2. see table 6.4 for the v rst-high specification.
rev. 1.1 53 c8051f54x table 6.6. internal high-frequency oscillator electrical characteristics v dd = 1.8 to 2.75 v, ?40 to +125 c unless otherwise specified; us ing factory-calibrated settings. parameter conditions min typ max units oscillator frequency ifcn = 111b; vdd > vregmin 1 ifcn = 111b; vdd < vregmin 1 24 ? 0.5% 24 ? 1.0% 24 2 24 2 24 + 0.5% 24 + 1.0% mhz oscillator supply current ? (from v dd ) internal oscillator on oscicn[7:6] = 11b ? 880 1300 a internal oscillator suspend oscicn[7:6] = 00b ztcen = 1 te m p = 2 5 c te m p = 8 5 c temp = 125 c ? 67 90 130 ? wake-up time from suspend oscicn[7:6] = 00b ? 1 ? s power supply sensitivity constant temperature ? 0.11 ? %/v temperature sensitivity 3 constant supply tc 1 tc 2 ? ? 5.0 ?0.65 ? ? ppm/c ppm/c 2 1. vregmin is the minimum out put of the voltage regulator for its low setting (reg0cn: reg0md = 0b). see table 6.8, ?voltage regulator electrical characteristics,? on page 54 . 2. this is the average frequency acro ss the operating temperature range 3. use temperature coefficients tc 1 and tc 2 to calculate the new internal oscillator frequency using the following equation: f(t) = f0 x (1 + tc 1 x (t - t0) + tc 2 x (t - t0) 2 ) where f0 is the internal oscillator frequency at 25 c and t0 is 25 c.
c8051f54x 54 rev. 1.1 table 6.7. clock multiplier electrical specifications v dd = 1.8 to 2.75 v, ?40 to +125 c unless otherwise specified. parameter conditions min typ max units input frequency (fcm in ) 2 ? ? mhz output frequency ? ? 50 mhz power supply current ? 0.9 1.9 ma table 6.8. voltage regulator electrical characteristics v dd = 1.8 to 2.75 v, ?40 to +125 c unless otherwise specified. parameter conditions min typ max units input voltage range (v regin )* 1.8* ? 5.25 v dropout voltage (v do ) maximum current = 50 ma ? 10 ? mv/ma output voltage (v dd ) 2.1 v operation (reg0md = 0) 2.6 v operation (reg0md = 1) 2.0 2.5 2.1 2.6 2.25 2.75 v bias current ? 1 9 a dropout indica tor detection threshold with respect to vdd ?0.21 ? ?0.02 v output voltage temperature coefficient ? 0.29 ? mv/c vreg settling time 50 ma load with v regin = 2.4 v and v dd load capacitor of 4.8 f ? 450 ? s *note: the minimum input voltage is 1.8 v or v dd + v do (max load), whichever is greater
rev. 1.1 55 c8051f54x table 6.9. adc0 electrical characteristics vdda = 1.8 to 2.75 v, ?40 to +125 c, vref = 1.5 v (refsl=0) unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity ? 0.5 3 lsb differential nonlinearity guaranteed monotonic ? 0.5 1 lsb offset error 1 ?10 3.0 10 lsb full scale error ?20 5.7 20 lsb offset temperature coefficient ? 7.7 ? ppm/c dynamic performance (10 khz sine-wave single-ended input, 1 db below full scale, 200 ksps) signal-to-noise plus distortion 63 65 ? db total harmonic distortion up to the 5th harmonic; ? 80 ? db spurious-free dynamic range ? -82 ? db conversion rate sar conversion clock ? ? 3.6 mhz conversion time in sar clocks 2 13 ? ? clocks track/hold acquisition time 3 vdda > 2.0 v vdda < 2.0 v 1.5 3.5 ? ? ? ? s throughput rate 4 vdda > 2.0 v ? ? 200 ksps analog inputs adc input voltage range 5 gain = 1.0 (default) gain = n 0 0 ? vref vref / n v absolute pin voltage with respect to gnd 0 ? v io v sampling capacitance ? 31 ? pf input multiplexer impedance ? 3 ? k ? power specifications power supply current ? (vdda supplied to adc0) operating mode, 200 ksps ? 1100 1500 a burst mode (idle) ? 1100 1500 a power-on time 5 ? ? s power supply rejection ? ?60 ? mv/v notes: 1. represents one standard deviation from the mean. of fset and full-scale error can be removed through calibration. 2. an additional 2 fclk cycles are requir ed to start and complete a conversion 3. additional tracking time may be required depending on the output impedance conn ected to the adc input. see section ? 5.2.1. settling time requirements ? on page 34 . 4. an increase in tracking time will decrease the adc throughput. 5. see section ? 5.3. selectable gain ? on page 35 for more information about the setting the gain.
c8051f54x 56 rev. 1.1 table 6.10. temperature sensor electrical characteristics vdda = 1.8 to 2.75 v, ?40 to +125 c unless otherwise specified. parameter conditions min typ max units linearity ? 0.1 ? c slope ? 3.33 ? mv/c slope error* ? 88 ? v/c offset te m p = 0 c ? 856 ? mv offset error* te m p = 0 c ? 14 ? mv power supply current ? 18 ? a tracking time 12 ? ? s *note: represents one standard deviation from the mean. table 6.11. voltage reference electrical characteristics vdda = 1.8 to 2.75 v, ?40 to +125 c unless otherwise specified. parameter conditions min typ max units internal reference (refbe = 1) output voltage 25 c ambient (reflv = 0) 1.45 1.50 1.55 v 25 c ambient (reflv = 1), v dd = 2.6 v 2.15 2.20 2.25 vref short-circuit current ? 5 10 ma vref temperature ? coefficient ? 38 ? ppm/c power consumption internal ? 30 50 a load regulation load = 0 to 200 a to agnd ? 3 ? v/a vref turn-on time 1 4.7 f tantalum and 0.1 f bypass ? 1.5 ? ms vref turn-on time 2 0.1 f bypass ? 46 ? s power supply rejection ? 1.2 ? mv/v external reference (refbe = 0) input voltage range 1.5 ? v dda v input current sample rate = 200 ksps; vref = 1.5 v ? 2.1 ? a power specifications reference bias generator refbe = 1 or tempe = 1 ? 21 40 a
rev. 1.1 57 c8051f54x table 6.12. comparator 0 and comparator 1 electrical characteristics vio = 1.8 to 5.25 v, ?40 to +125 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm * = 1.5 v cpn+ ? cpn? = 100 mv ? 330 ? ns cpn+ ? cpn? = ?100 mv ? 390 ? ns response time: mode 1, vcm * = 1.5 v cpn+ ? cpn? = 100 mv ? 490 ? ns cpn+ ? cpn? = ?100 mv ? 610 ? ns response time: mode 2, vcm * = 1.5 v cpn+ ? cpn? = 100 mv ? 590 ? ns cp0+ ? cp0? = ?100 mv ? 750 ? ns response time: mode 3, vcm * = 1.5 v cpn+ ? cpn? = 100 mv ? 2300 ? ns cpn+ ? cpn? = ?100 mv ? 3100 ? ns common-mode rejection ratio ? 2.1 13 mv/v positive hysteresis 1 cpnhyp1?0 = 00 ?2 0 2 mv positive hysteresis 2 cpnhyp1?0 = 01 2 6 10 mv positive hysteresis 3 cpnhyp1?0 = 10 5 11 20 mv positive hysteresis 4 cpnhyp1?0 = 11 13 21 40 mv negative hysteresis 1 cpnhyn1?0 = 00 ?2 0 2 mv negative hysteresis 2 cpnhyn1?0 = 01 2 5 10 mv negative hysteresis 3 cpnhyn1?0 = 10 5 11 20 mv negative hysteresis 4 cpnhyn1?0 = 11 13 21 40 mv inverting or non- inverting input voltage range ?0.25 ? v io + 0.25 v input capacitance ? 8 ? pf input offset voltage ?10 ? +10 mv power supply power supply rejection ? 0.18 ? mv/v power-up time ? 3 ? s supply current at dc mode 0 ? 6.3 20 a mode 1 ? 3.4 10 a mode 2 ? 2.6 7.5 a mode 3 ? 0.6 3 a *note: vcm is the common-mode voltage on cp0+ and cp0?.
c8051f54x 58 rev. 1.1 6.1. adc0 analog multiplexer adc0 includes an analog multiplexer to enable multiple analog input sources. any of the following may be selected as an input: p0.0 ? p3.0, the on-chip temperature s ensor, the core power supply (v dd ), or ground (gnd). adc0 is single-ended and all signals measured are with respect to gnd. the adc0 input channels are selected using the adc0mx regi ster as described in sfr definition 6.3. figure 6.2. adc0 multiplexer block diagram important note about adc0 input configuration: port pins selected as adc0 inputs should be config- ured as analog inputs, and should be skipped by the digital crossbar. to configure a port pin for analog input, set to 0 the corresponding bit in register pnmdin. to force the crossbar to skip a port pin, set to 1 the corresponding bit in register pnskip. see section ?18. port input/output? on page 147 for more port i/o configuration details. adc0 temp sensor amux vdd adc0mx adc0mx5 adc0mx4 adc0mx3 adc0mx2 adc0mx1 adc0mx0 p0.0 p2.2-p2.7, p3.0 only available on 32-pin packages gnd p0.7 p1.0 p1.7 p2.0 p2.7 p3.0
rev. 1.1 59 c8051f54x sfr address = 0xbb; sfr page = 0x00; sfr definition 6.3. adc0mx: adc0 channel select bit 7 6 5 4 3 2 1 0 name adc0mx[5:0] type r r r/w reset 0 0 1 1 1 1 1 1 bit name function 7:6 unused read = 00b; write = don?t care. 5:0 amx0p[5:0] amux0 positive input selection. 000000: p0.0 000001: p0.1 000010: p0.2 000011: p0.3 000100: p0.4 000101: p0.5 000110: p0.6 000111: p0.7 001000: p1.0 001001: p1.1 001010: p1.2 001011: p1.3 001100: p1.4 001101: p1.5 001110: p1.6 001111: p1.7 010000: p2.0 010001: p2.1 010010: p2.2 (only available on 32-pin package devices) 010011: p2.3 (only available on 32-pin package devices) 010100: p2.4 (only available on 32-pin package devices) 010101: p2.5 (only available on 32-pin package devices) 010110: p2.6 (only available on 32-pin package devices) 010111: p2.7 (only available on 32-pin package devices) 011000: p3.0 (only available on 32-pin package devices) 011001 ? 101111: reserved 110000: temp sensor 110001: v dd 110010 ? 111111: gnd
c8051f54x 60 rev. 1.1 6.2. temperature sensor an on-chip temperature sensor is included on the c8 051f54x devices which can be directly accessed via the adc multiplexer in single-ended configuration. to use the adc to measure the temperature sensor, the adc multiplexer channel should be configured to connect to the temperature sensor. the temperature sensor transfer function is shown in figure 6.3. the output voltage (v temp ) is the positive adc input is selected by bits ad0mx[4:0] in register adc0mx . the tempe bit in regist er ref0cn enables/disables the temperature sensor, as described in sfr defini tion 7.1. while disabled, the temperature sensor defaults to a high impedance state and any adc meas urements performed on the sensor will result in meaningless data. refer to table 6.10 for the slope and offset parameters of the temperature sensor. figure 6.3. temperature sensor transfer function temperature voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope
rev. 1.1 61 c8051f54x 7. voltage reference the voltage reference multiplexer on the c8051f54x de vices is configurable to use an externally con- nected voltage reference, the on-chip reference vo ltage generator routed to the vref pin, or the v dd power supply voltage (see figure 7.1). the refsl bit in the reference control register (ref0cn, sfr definition 7.1) selects the reference source for the a dc. for an external source or the on-chip reference, refsl should be set to 0 to select the vref pin. to use v dd as the reference source, refsl should be set to 1. the biase bit enables th e internal voltage bi as generator, which is used by the adc, temperature sensor, and internal oscillator. this bias is automatically enabled when any peripheral which requires it is enabled, and it does not need to be enabled manually. the bi as generator may be enabled manually by writing a 1 to the biase bit in register ref0cn. the electrical specifications for th e voltage reference circuit are given in table 6.11. the on-chip voltage reference circuit consists of a temperature stable bandgap voltage reference genera- tor and a gain-of-two output buffer amplifier. the output voltage is selectable between 1.5 v and 2.25 v. the on-chip voltage reference can be driven on the vref pin by setting the refbe bit in register ref0cn to a 1. the maximum load seen by the vref pin must be less than 200 a to gnd. bypass capacitors of 0.1 f and 4.7 f are recommended from the vref pi n to gnd. if the on-chip reference is not used, the refbe bit should be cleared to 0. elec trical specifications for the on-ch ip voltage reference are given in table 6.11. important note about the vref pin: when using either an external vo ltage reference or the on-chip ref- erence circuitry, the vref pin should be configured as an analog pin and skipped by the digital crossbar. refer to section ?18. port input/output? on page 147 for the location of the vref pin, as well as details of how to configure the pin in analog mode and to be skipped by the crossbar. figure 7.1. voltage reference functional block diagram vref (to adc) to analog mux vdd vref r1 vdd external voltage reference circuit gnd temp sensor en bias generator to adc, internal oscillators en iosce n 0 1 ref0cn refsl tempe biase refbe refbe internal reference en recommended bypass capacitors + 4.7 ? f0.1 ? f
c8051f54x 62 rev. 1.1 sfr address = 0xd1; sfr page = 0x00 sfr definition 7.1. ref0cn: reference control bit 7 6 5 4 3 2 1 0 name ztcen reflv refsl tempe biase refbe type r r r r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:6 unused read = 00b; write = don?t care. 5 ztcen zero temperature coefficient bias enable bit. this bit must be set to 1b befo re entering oscillator suspend mode. 0: zerotc bias generator automa tically enabled when required. 1: zerotc bias generator forced on. 4 reflv voltage reference output level select. this bit selects the output voltage level for the internal voltage reference 0: internal voltage reference set to 1.5 v. 1: internal voltage reference set to 2.20 v. 3 refsl voltage reference select. this bit selects the adcs voltage reference. 0: v ref pin used as voltage reference. 1: v dd used as voltage reference. 2 tempe temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. 1 biase internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. 0 refbe on-chip reference buffer enable bit. 0: on-chip reference buffer off. 1: on-chip reference buffer on. internal voltage reference driven on the v ref pin.
rev. 1.1 63 c8051f54x 8. comparators the c8051f54x devices include two on-chip programma ble voltage comparators. a block diagram of the comparators is shown in figure 8.1, where ?n? is the comparator number (0 or 1). the two comparators operate identically except that comparator0 can also be used a re set source. for input selection details, refer to sfr definition 8.5 and sfr definition 8.6. each comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the port pins : a synchronous ?latched? output (cp0, cp1), or an asynchronous ?raw? output (cp0a, cp1a). the asynchronous signal is available even when the system clock is not active. this allows the comparators to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator outputs may be configured as open drain or push-pull (see section ?18.4. port i/o initialization? on page 152). comparator0 may also be used as a reset source (see section ?16.5. comparator0 reset? on page 133). the comparator0 inputs are selected in the cpt0mx register (sfr definition 8.5). the cmx0p1-cmx0p0 bits select the comparator0 positive input; the cmx0n1-cmx0n0 bits select the comparator0 negative input. the comparator1 inputs are selected in the cp t1mx register (sfr definition 8.6). the cmx1p1- cmx1p0 bits select the comparator1 positive inpu t; the cmx1n1-cmx1n0 bits select the comparator1 negative input. important note about comparator inputs: the port pins selected as comparator inputs should be con- figured as analog inputs in their associated port co nfiguration register, and configured to be skipped by the crossbar (for details on port configuration, see section ?18.1. port i/o modes of operation? on page 148). figure 8.1. comparator functional block diagram vio reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cpn + cpn - cptnmd cpnrie cpnfie cpnmd1 cpnmd0 cpn cpna cpn interrupt 0 1 0 1 cpnrif cpnfif 0 1 cpnen 0 1 ea comparator input mux cptncn cpnen cpnout cpnrif cpnfif cpnhyp1 cpnhyp0 cpnhyn1 cpnhyn0
c8051f54x 64 rev. 1.1 comparator outputs can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, compar ator outputs are availa ble asynchronous or syn chronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis- abled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and the power supply to the comparat or is turned off. see section ?18.3. priority crossbar decoder? on page 150 for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator elec- trical specifications are given in table 6.12. the comparator response time may be configured in software via the cptnmd registers (see sfr defini- tion 8.2). selecting a longer response time reduces the comparator supply current. see table 6.12 for complete timing and supply current requirements. figure 8.2. comparator hysteresis plot comparator hysteresis is software-programmable via its comparator control register cptncn. the amount of negative hyst eresis voltage is determined by the setti ngs of the cpnhyn bits. as shown in figure 8.2, various levels of nega tive hysteresis can be programmed, or negative hysteresis can be dis- abled. in a similar way, the amount of positive hysteresis is determined by the setting the cpnhyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter- rupt enable and priority control, see ?13. interrupts? .) the cpnfif flag is set to 1 upon a comparator fall- ing-edge, and the cpnrif flag is set to 1 upon the comparator rising-edge. once set, these bits remain set until cleared by software. the output state of the comparator can be obtained at any time by reading the cpnout bit. the comparator is enabled by setting th e cpnen bit to 1, and is disabled by clearing this bit to 0. positive hysteresis voltage (programmed with cpnhyp bits) negative hysteresis voltage (programmed by cpnhyn bits) vin- vin+ inputs circuit configuration + _ cpn+ cpn- cpn vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol
rev. 1.1 65 c8051f54x note that false rising ed ges and falling edges can be detected when the comparator is fi rst powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a sh ort time after the comparator is enabled or its mode bits have been changed. sfr address = 0x9a; sfr page = 0x00 sfr definition 8.1. cpt0cn: comparator0 control bit 7 6 5 4 3 2 1 0 name cp0en cp0out cp0rif cp0fif cp0hyp[1:0] cp0hyn[1:0] type r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cp0en comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. 6 cp0out comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . 5 cp0rif comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occurred since this flag was last cleared. 1: comparator0 rising edge has occurred. 4 cp0fif comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-edge has occu rred since this flag was last cleared. 1: comparator0 falling- edge has occurred. 3:2 cp0hyp[1:0] comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp0hyn[1:0] comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
c8051f54x 66 rev. 1.1 sfr address = 0x9b; sfr page = 0x00 sfr definition 8.2. cpt0md: comparator0 mode selection bit 7 6 5 4 3 2 1 0 name cp0rie cp0fie cp0md[1:0] type r r r/w r/w r r r/w reset 0 0 0 0 0 0 1 0 bit name function 7:6 unused read = 00b, write = don?t care. 5 cp0rie comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. 4 cp0fie comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge inte rrupt disabled. 1: comparator0 falling-edge inte rrupt enabled. 3:2 unused read = 00b, write = don?t care. 1:0 cp0md[1:0] comparator0 mode select. these bits affect the response time and power consumption for comparator0. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
rev. 1.1 67 c8051f54x sfr address = 0x9d; sfr page = 0x00 sfr definition 8.3. cpt1cn: comparator1 control bit 7 6 5 4 3 2 1 0 name cp1en cp1out cp1rif cp1fif cp1hyp[1:0] cp1hyn[1:0] type r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cp1en comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. 6 cp1out comparator1 output state flag. 0: voltage on cp1+ < cp1 ? . 1: voltage on cp1+ > cp1 ? . 5 cp1rif comparator1 rising-edge flag. must be cleared by software. 0: no comparator1 rising edge has occurred since this flag was last cleared. 1: comparator1 rising edge has occurred. 4 cp1fif comparator1 falling-edge flag. must be cleared by software. 0: no comparator1 falling-edge has occu rred since this flag was last cleared. 1: comparator1 falling- edge has occurred. 3:2 cp1hyp[1:0] comparator1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp1hyn[1:0] comparator1 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
c8051f54x 68 rev. 1.1 sfr address = 0x9e; sfr page = 0x00 sfr definition 8.4. cpt1md: comparator1 mode selection bit 7 6 5 4 3 2 1 0 name cp1rie cp1fie cp1md[1:0] type r r r/w r/w r r r/w reset 0 0 0 0 0 0 1 0 bit name function 7:6 unused read = 00b, write = don?t care. 5 cp1rie comparator1 rising-edge interrupt enable. 0: comparator1 rising-edge interrupt disabled. 1: comparator1 rising-edge interrupt enabled. 4 cp1fie comparator1 falling-edge interrupt enable. 0: comparator1 falling-edge inte rrupt disabled. 1: comparator1 falling-edge inte rrupt enabled. 3:2 unused read = 00b, write = don?t care. 1:0 cp1md[1:0] comparator1 mode select. these bits affect the response time and power consumption for comparator1. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
rev. 1.1 69 c8051f54x 8.1. comparator multiplexer c8051f54x devices include an analog input multiplexer for each of the comparators to connect port i/o pins to the comparator inputs. the comparator0 inputs are selected in the cpt0mx register (sfr defini- tion 8.5). the cmx0p3 ? cmx0p0 bits select the comparator0 positive input; the cmx0n3 ? cmx0n0 bits select the comparator0 negative input. similarly, the comparator1 inputs are selected in the cpt1mx reg- ister using the cmx1p3-cmx1p0 bits and cmx1n3-cmx 1n0 bits. the same pins are available to both multiplexers at the same time and can be used by both comparators simultaneously. important note about comparator inputs: the port pins selected as comparator inputs should be con- figured as analog inputs in their associated port co nfiguration register, and configured to be skipped by the crossbar (for details on port configuration, see se ction ?18.6. special function registers for accessing and configuring port i/o? on page 161). figure 8.3. comparator input multiplexer block diagram vdd + - gnd cpn + cpn - p0.1 p0.3 p0.5 p0.7 cptnmx cmxnn3 cmxnn2 cmxnn1 cmxnn0 cmxnp3 cmxnp2 cmxnp1 cmxnp0 p1.1 p1.3 p1.5 p1.7 p2.1 p2.3 p2.5 p2.7 p0.0 p0.2 p0.4 p0.6 p1.0 p1.2 p1.4 p1.6 p2.0 p2.2 p2.4 p2.6
c8051f54x 70 rev. 1.1 sfr address = 0x9c; sfr page = 0x00 sfr definition 8.5. cpt0mx: comparator0 mux selection bit 7 6 5 4 3 2 1 0 name cmx0n[3:0] cmx0p[3:0] type r/w r/w reset 0 1 1 1 0 1 1 1 bit name function 7:4 cmx0n[3:0] comparator0 negative input mux selection. 0000: p0.1 0001: p0.3 0010: p0.5 0011: p0.7 0100: p1.1 0101: p1.3 0110: p1.5 0111: p1.7 1000: p2.1 1001: p2.3 (only available on 32-pin devices) 1010: p2.5 (only available on 32-pin devices) 1011: p2.7 (only available on 32-pin devices) 1100?1111: none 3:0 cmx0p[3:0] comparator0 positive input mux selection. 0000: p0.0 0001: p0.2 0010: p0.4 0011: p0.6 0100: p1.0 0101: p1.2 0110: p1.4 0111: p1.6 1000: p2.0 1001: p2.2 (only available on 32-pin devices) 1010: p2.4 (only available on 32-pin devices) 1011: p2.6 (only available on 32-pin devices) 1100?1111: none
rev. 1.1 71 c8051f54x sfr address = 0x9f; sfr page = 0x00 sfr definition 8.6. cpt1mx: comparator1 mux selection bit 7 6 5 4 3 2 1 0 name cmx1n[3:0] cmx1p[3:0] type r/w r/w reset 0 1 1 1 0 1 1 1 bit name function 7:4 cmx1n[3:0] comparator1 negative input mux selection. 0000: p0.1 0001: p0.3 0010: p0.5 0011: p0.7 0100: p1.1 0101: p1.3 0110: p1.5 0111: p1.7 1000: p2.1 1001: p2.3 (only available on 32-pin devices) 1010: p2.5 (only available on 32-pin devices) 1011: p2.7 (only available on 32-pin devices) 1100?1111: none 3:0 cmx1p[3:0] comparator1 positive input mux selection. 0000: p0.0 0001: p0.2 0010: p0.4 0011: p0.6 0100: p1.0 0101: p1.2 0110: p1.4 0111: p1.6 1000: p2.0 1001: p2.2 (only available on 32-pin devices) 1010: p2.4 (only available on 32-pin devices) 1011: p2.6 (only available on 32-pin devices) 1100?1111: none
c8051f54x 72 rev. 1.1 9. voltage regulator (reg0) c8051f54x devices include an on-chip low dropout vo ltage regulator (reg0). the input to reg0 at the v regin pin can be as high as 5.25 v. the output can be selected by software to 2.1 v or 2.6 v. when enabled, the output of reg0 appears on the v dd pin, powers the microcontroller core, and can be used to power external devices. on reset, reg0 is enabled and can be disabled by software. the voltage regulator can generate an interrupt (if enabl ed by ereg0, eie2.0) that is triggered whenever the v regin input voltage drops below the dropout threshold voltage. this dropout interrupt has no pending flag and the recommended procedure to use it is as follows: 1. wait enough time to ensure the v regin input voltage is stable 2. enable the dropout interrupt (ereg0, eie2.0) and select the proper priority (preg0, eip2.0) 3. if triggered, inside the interrupt disable it (clear ereg0, eie2.0), execute al l procedures necessary to protect your application (put it in a safe mode and leave the interrupt now disabled). 4. in the main application, now running in the safe mode, regularly check the dropout bit (reg0cn.0). once it is cleared by the regula tor hardware, the application can enable the interrupt again (ereg0, eie1.6) and return to the normal mode operation. the input (v regin ) and output (v dd ) of the voltage regulator should both be bypassed with a large capaci- tor (4.7 f + 0.1 f) to ground as shown in figure 9.1 below. this capacitor will eliminate power spikes and provide any immediate power required by the micr ocontroller. the settling time associated with the voltage regulator is shown in table 6.8 on page 54. figure 9.1. external capacitors for voltage regulator input/output? regulator enabled if the internal voltage regu lator is not used, the v regin input should be tied to v dd , as shown in figure 9.2. v dd v dd reg0 4.7 f 4.7 f .1 f .1 f v regin
rev. 1.1 73 c8051f54x figure 9.2. external capacitors for voltage regulator input/output?regulator disabled sfr address = 0xc9; sfr page = 0x00 sfr definition 9.1. reg0cn: regulator control bit 7 6 5 4 3 2 1 0 name regdis reserved reg0md dropout type r/w r/w r r/w r r r r reset 0 1 0 1 0 0 0 0 bit name function 7 regdis voltage regulator disable bit. 0: voltage regulator enabled 1: voltage regulator disabled 6 reserved read = 1b; must write 1b. 5 unused read = 0b; write = don?t care. 4 reg0md voltage regulator mode select bit. 0: voltage regulator output is 2.1v. 1: voltage regulator output is 2.6v. 3:1 unused read = 000b. write = don?t care. 0 dropout voltage regulator dropout indicator. 0: voltage regulator is not in dropout 1: voltage regulator is in or near dropout. v regin v dd v dd 4.7 f .1 f
c8051f54x 74 rev. 1.1 10. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. the mcu family has a superset of all the peri pherals included with a standard 8051. the cip-51 also includes on-chip debug hardware (see descriptio n in section 25), and interfaces directly with the ana- log and digital subsystems providing a complete data acqu isition or control-system so lution in a single inte- grated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (s ee figure 10.1 for a block diagram). the cip-51 includes the following features: ? fully compatible with mcs-51 instruction set ? 50 mips peak throughput with 50 mhz clock ? 0 to 50 mhz clock frequency ? extended interrupt handler ? reset input ? power management modes ? on-chip debug logic ? program and data memory security ? 10.1. performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standar d 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles.
rev. 1.1 75 c8051f54x figure 10.1. cip-51 block diagram with the cip-51's maximum system clock at 50 mhz, it has a peak throughput of 50 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu- tion time. programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the silicon l abs 2-wire development interface (c2). the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem- ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or other on-chip resources. c2 details can be foun d in section ?25. c2 interface? on page 269. the cip-51 is support ed by development tools from silicon labs and third party vendors. silicon labs pro- vides an integrated development environment (ide) in cluding editor, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast and efficient in-sys- tem device programming and debugging. third party macro assemblers and c compilers are also avail- able. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8
c8051f54x 76 rev. 1.1 10.2. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc- tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan- dard 8051. 10.2.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instruction ti mings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as oppo sed to when the branch is taken. table 10.1 is the cip-51 instruction set summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
rev. 1.1 77 c8051f54x table 10.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 note: certain instructions take a variable number of clock cycles to execute depending on instruction alignment and the flrt setting ( sfr definition 14.3 ).
c8051f54x 78 rev. 1.1 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 table 10.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles note: certain instructions take a variable number of clock cycles to execute depending on instruction alignment and the flrt setting (sfr definition 14.3).
rev. 1.1 79 c8051f54x setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3* jnc rel jump if carry is not set 2 2/3* jb bit, rel jump if direct bit is set 3 3/4* jnb bit, rel jump if direct bit is not set 3 3/4* jbc bit, rel jump if direct bit is set and clear bit 3 3/4* program branching acall addr11 absolute subroutine call 2 3* lcall addr16 long subroutine call 3 4* ret return from subroutine 1 5* reti return from interrupt 1 5* ajmp addr11 absolute jump 2 3* ljmp addr16 long jump 3 4* sjmp rel short jump (relative address) 2 3* jmp @a+dptr jump indirect relative to dptr 1 3* jz rel jump if a equals zero 2 2/3* jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 4/5* cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4* cjne rn, #data, rel compare immediate to register and jump if not equal 3 3/4* cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 4/5* djnz rn, rel decrement register and jump if not zero 2 2/3* djnz direct, rel decrement direct byte and jump if not zero 3 3/4* nop no operation 1 1 table 10.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles note: certain instructions take a variable number of clock cycles to execute depending on instruction alignment and the flrt setting (sfr definition 14.3).
c8051f54x 80 rev. 1.1 10.3. cip-51 re gister descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic l. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's defa ult state. detailed descriptions of the remaining sfrs are included in the sections of the datasheet associated with their corresponding sys- tem function. notes on registers, operands and addressing modes: rn ?register r0?r7 of the currently selected register bank. @ri ?data ram location addressed indirectly through r0 or r1. rel ?8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct ?8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data ?8-bit constant #data16 ?16-bit constant bit ?direct-accessed bit in data ram or sfr addr11 ?11-bit destination address used by acall and ajmp. the destination must be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 ?16-bit destination address used by lcall an d ljmp. the destination may be anywhere within the 64 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
rev. 1.1 81 c8051f54x sfr address = 0x82; sfr page = all pages sfr address = 0x83 ; sfr page = all pages sfr definition 10.1. dpl: data pointer low byte bit 7 6 5 4 3 2 1 0 name dpl[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16 -bit dptr. dptr is used to access indi - rectly addressed flash memory or xram. sfr definition 10.2. dph: data pointer high byte bit 7 6 5 4 3 2 1 0 name dph[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dptr. dptr is used to access indi - rectly addressed flash memory or xram.
c8051f54x 82 rev. 1.1 sfr address = 0x81; sfr page = all pages sfr address = 0xe0; sfr page = all pages; bi t-addressable sfr address = 0xf0; sfr page = all pages; bit-addressable sfr definition 10.3. sp: stack pointer bit 7 6 5 4 3 2 1 0 name sp[7:0] type r/w reset 0 0 0 0 0 1 1 1 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the to p of the stack. the stack pointer is incre - mented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 10.4. acc: accumulator bit 7 6 5 4 3 2 1 0 name acc[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations. sfr definition 10.5. b: b register bit 7 6 5 4 3 2 1 0 name b[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 b[7:0] b register. this register serves as a second accumu lator for certain arithmetic operations.
rev. 1.1 83 c8051f54x sfr address = 0xd0; sfr page = all pages; bit-addressable sfr definition 10.6. psw: program status word bit 7 6 5 4 3 2 1 0 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 0 0 0 0 0 0 0 0 bit name function 7 cy carry flag. this bit is set when the last arithmetic oper ation resulted in a carry (addition) or a bor - row (subtraction). it is cleared to logi c 0 by all other arithmetic operations. 6 ac auxiliary carry flag. this bit is set when the last arithmetic operat ion resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith - metic operations. 5 f0 user flag 0. this is a bit-addressable, general purp ose flag for use under software control. 4:3 rs[1:0] register bank select. these bits select which register bank is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2 ov overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instruction causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, a ddc, subb, mul, and div instructions in all other cases. 1 f1 user flag 1. this is a bit-addressable, general purp ose flag for use under software control. 0 parity parity flag. this bit is set to logic 1 if the sum of the ei ght bits in the accumulator is odd and cleared if the sum is even.
c8051f54x 84 rev. 1.1 10.4. serial number spec ial function registers (sfrs) the c8051f54x devices include four sfrs, sn0 through sn3, that are pre-programmed during production with a unique, 32-bit serial number. the serial number provides a unique identification number for each device and can be read from the application firmware. if the serial number is not used in the application, these four registers can be used as general purpose sfrs. sfr addresses: sn0 = 0xf9; sn1 = 0xfa; sn2 = 0xfb; sn3 = 0xfc; sfr page = 0x0f; sfr definition 10.7. snn: serial number n bit 7 6 5 4 3 2 1 0 name sernumn[7:0] type r/w reset varies?unique 32-bit value bit name function 7:0 sernumn[7:0] serial number bits. the four serial number registers form a 32-bit serial number, with sn3 as the most significant byte and sn0 as the least significant byte.
rev. 1.1 85 c8051f54x 11. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different inst ruction types. the memory organization is shown in figure 11.1 figure 11.1. c8051f54x memory map 11.1. program memory the cip-51 core has a 64 kb program memory space. the c8051f54x devices implement 16 kb or 8 kb of this program memory space as in-system, re-pro grammable flash memory, organized in a contiguous block from addresses 0x0000 to 0x3fff in 16 kb devices and addresses 0x0000 to 0x1fff in 8 kb devices. the address 0x3bff in 16 kb devices and 0x1fff in 8 kb devices serves as the security lock byte for the device. addresses above 0x3bff are reserved in the 16 kb devices. program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space 0x0000 0x03ff same 1024 bytes as from 0x0000 to 0x03ff, wrapped on 1024-byte boundaries 0x0400 0xffff 16 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x3c00 0x3bff c8051f540/1/2/3 8 kb flash (in-system programmable in 512 byte sectors) 0x0000 0x1fff c8051f544/5/6/7 xram 1k bytes (accessable using movx instruction)
c8051f54x 86 rev. 1.1 figure 11.2. flash program memory map 11.1.1. movx instruction and program memory the movx instruction in an 8051 device is typica lly used to access external data memory. on the c8051f54x devices, the movx instruction is normally used to read and write on-chip xram, but can be re-configured to write and erase on-chip flash memory space. movc instructions are always used to read flash memory, while movx write instructions are used to erase and write flash. this flash access feature provides a mechanism for the c8051f54x to update pr ogram code and use the program memory space for non-volatile data storage. refer to section ?14. flash memory? on page 117 for further details. 11.2. data memory the c8051f54x devices include 1280 bytes of ram dat a memory. 256 bytes of this memory is mapped into the internal ram space of the 8051. the other 10 24 bytes of this memory is on-chip ?external? mem- ory. the data memory map is shown in figure 11.1 for reference. 11.2.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for genera l purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 byte s, locations 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instructio n when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data me mory. figure 11.1 illustrate s the data memory organi zation of the c8051f54x. lock byte 0x0000 0x1fff 0x1ffe flash memory organized in 512-byte pages 0x1e00 flash memory space (8 kb flash device) lock byte page lock byte 0x0000 0x3bff 0x3bfe 0x3c00 0x3a00 flash memory space (16 kb flash device) lock byte page 0x3fff reserved area c8051f540/1/2/3 c8051f544/5/6/7
rev. 1.1 87 c8051f54x 11.2.1.1. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen- eral-purpose registers. each bank consists of eigh t byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see descri ption of the psw in sfr de finition 10.6). this allows fast context switching when entering subroutines and in terrupt service routines. indirect addressing modes use registers r0 and r1 as index registers. 11.2.1.2. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina- tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 11.2.1.3. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig- nated using the stack pointer (sp) sfr. the sp will point to the last lo cation used. the next value pushed on the stack is placed at sp+1 and then sp is incremen ted. a reset initializes the stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis- ter (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 11.3. external ram for c8051f54x devices, 1 kb of ram are included on -chip and mapped into the external data memory space (xram). the external memory space may be accessed using the external move instruction (movx) and the data pointer (dptr), or using the movx in direct addressing mode using r0 or r1. if the movx instruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit address is provided by the external memory interface control re gister (emi0cn, shown in sfr definition 11.1). note: the movx instruction can also be used for writing to the flash memory. see section ? 14. flash memory ? on page 117 for details. the movx instruction accesses xram by default. 11.3.1. 16-bit movx example the 16-bit form of the movx instructi on accesses the memory location po inted to by the contents of the dptr register. the following series of instructions reads the value of the byte at address 0x1234 into the accumulator a: mov dptr, #1234h ; load dptr with 16-bit address to read (0x1234) movx a, @dptr ; load contents of 0x1234 into accumulator a ? the above example uses the 16-bit immediate mov instruction to set th e contents of dptr. alternately,
c8051f54x 88 rev. 1.1 the dptr can be accessed through the sfr registers dph, which contains the upper 8-bits of dptr, and dpl, which contains the lower 8-bits of dptr. 11.3.2. 8-bit movx example the 8-bit form of the movx instruction uses the content s of the emi0cn sfr to determine the upper 8-bits of the effective address to be accessed and the contents of r0 or r1 to determine the lower 8-bits of the effective address to be accessed. the following series of instructions read the contents of the byte at address 0x1234 into the accumulator a. mov emi0cn, #12h ; load high byte of address into emi0cn mov r0, #34h ; load low byte of address into r0 (or r1) movx a, @r0 ; load contents of 0x1234 into accumulator a sfr address = 0xaa; sfr page = 0x00 sfr definition 11.1. emi0cn: external memory interface control bit 7 6 5 4 3 2 1 0 name pgsel[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pgsel[7:0] xram page select bits. the xram page select bits provide the high byte of the 16-bit external data memory address when using an 8-bit movx command, ef fectively selecting a 256-byte page of ram. 0x00: 0x0000 to 0x00ff 0x01: 0x0100 to 0x01ff ... 0xfe: 0xfe00 to 0xfeff 0xff: 0xff00 to 0xffff
rev. 1.1 89 c8051f54x 12. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchan ge with the c8051f54x's resources and peripherals. the cip-51 controller core duplicates the sfrs found in a typical 8051 implementation as well as imple- menting additional sfrs used to configure and acce ss the sub-systems unique to the c8051f54x. this allows the addition of new functi onality while retaining compatibility with the mcs-51? instruction set. table 12.2 lists the sfrs implemented in the c8051f54x device family. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g., p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all othe r sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing unoccupied addresses in the sfr space will have an indeterminate effect and should be avoided. refer to the corresponding pages of the data sheet, as indicated in table 12.2, for a detailed description of each register. 12.1. sfr paging the cip-51 features sfr paging , allowing the device to map many sfrs into the 0x80 to 0xff memory address space. the sfr memory space has 256 pages . in this way, each memory location from 0x80 to 0xff can access up to 256 sfrs. the c8051f54x fa mily of devices utilizes two sfr pages: 0x00 and 0x0f. sfr pages are selected using the special func tion register page sele ction register, sfrpage (see sfr definition 11.3). the procedure for reading and writing an sfr is as follows: 1. select the appropriate sfr page number using the sfrpage register. 2. use direct accessing mode to read or write t he special function register (mov instruction). 12.2. interrupts and sfr paging when an interrupt occurs, the sfr p age register will automatically switch to the sfr page containing the flag bit that caused the interrupt. the automatic sfr page switch function conveniently removes the bur- den of switching sfr pages from the interrupt service ro utine. upon execut ion of the reti instruction, the sfr page is automatically restored to the sfr page in use prior to the interrupt. this is accomplished via a three-byte sfr page stack . the top byte of the stack is sfrpag e, the current sfr page. the second byte of the sfr page stack is sfrnext. the third, or bottom byte of the sfr page stack is sfrlast. upon an interrupt, the current sfrpage value is pushed to the sfrnext byte, and the value of sfrnext is pushed to sfrlast. hardware then loads sfrpage with the sfr page containing the flag bit associated with the interrupt. on a return from in terrupt, the sfr page stack is popped resulting in the value of sfrnext returning to the sfrpage regist er, thereby restoring the sfr page context without software intervention. the value in sfrlast (0x00 if there is no sfr page value in the bottom of the stack) of the stack is placed in sfrnext register. if desired, the values stored in sfrnext and sfr- last may be modified during an interrupt, enabling the cpu to return to a different sfr page upon exe- cution of the reti instruction (on in terrupt exit). modifying registers in the sfr page stack does not cause a push or pop of the st ack. only interrupt calls and returns will cause push/ pop operations on the sfr page stack. on the c8051f54x devices, vectoring to an interrupt will switch sf rpage to page 0x00.
c8051f54x 90 rev. 1.1 figure 12.1. sfr page stack automatic hardware switching of the sfr page on interrupts may be enabled or disabled as desired using the sfr automatic page control enab le bit located in the sfr page control register (sfr0cn). this function defaults to ?enabled? upon reset. in this way, the autoswitching functi on will be enabled unless dis- abled in software. a summary of the sfr locations (address and sfr page) are provided in table 12.2 in the form of an sfr memory map. each memory location in the map has an sfr page row, denoting the page in which that sfr resides. certain sfrs are acce ssible from all sfr pages, and are denoted by the ?(all pages)? designation. for example, the port i/o registers p0, p1, p2, and p3 all have the ?(all pages)? designa- tion, indicating these sfrs are accessible from all sfr pages regardless of the sfrpage register value. sfrnext sfrpage sfrlast cip-51 interrupt logic sfrpgcn bit
rev. 1.1 91 c8051f54x 12.3. sfr page stack example the following is an example that shows the operation of the sfr page stack during interrupts. in this example, the sfr control register is left in the de fault enabled state (i.e., sfrpgen = 1), and the cip-51 is executing in-line code that is writing values to smbus address register (sfr ?smb0adr?, located at address 0xb9 on sfr page 0x0f). the device is also using the spi peripheral (spi0) and the programma- ble counter array (pca0) peripheral to generate a pwm output. the pca is timing a critical control func- tion in its interrupt se rvice routine, and so its associated isr is set to high priority. at this point, the sfr page is set to access the smb0adr sfr (sfrpage = 0x0f). see figure 12.2. figure 12.2. sfr page stack while using sfr page 0x0 to access smb0adr while cip-51 executes in-line code (writing a value to smb0adr in this example), the spi0 interrupt occurs. the cip-51 vectors to the spi0 isr and pushes the current sfr page value (sfr page 0x0f) into sfrnext in the sfr page stack. the sfr page needed to access spi0?s sfrs is then automatically placed in the sfrpage register (sfr page 0x00). sfrpage is considered the ?top? of the sfr page stack. software can now access th e spi0 sfrs. software may switch to any sfr page by writing a new value to the sfrpage register at any time during th e spi0 isr to access sfrs that are not on sfr page 0x00. see figure 12.3. 0x0f (smb0adr) sfrpage sfrlast sfrnext sfr page stack sfr's
c8051f54x 92 rev. 1.1 figure 12.3. sfr page stack after spi0 interrupt occurs while in the spi0 isr, a pca inte rrupt occurs. recall the pca interrupt is configured as a high priority interrupt, while the spi0 inte rrupt is configured as a low priority interrup t. thus, the cip-51 will now vector to the high priority pca isr. upon doing so, the cip-51 will automatically plac e the sfr page needed to access the pca?s special function registers into the sfrpage register, sfr page 0x00. the value that was in the sfrpage register before the pca interrupt (sfr page 0x00 for spi00) is pushed down the stack into sfrnext. likewise, the value that was in the sfrnext register before the pca interrupt (in this case sfr page 0x0f for smb0adr) is pushed down to the sfrlast register, the ?bottom? of the stack. note that a value st ored in sfrlast (via a previous softwa re write to the sfrlast register) will be overwritten. see figure 12.4. 0x00 (spi0) 0x0f (smb0adr) sfrpage sfrlast sfrnext sfrpage pushed to sfrnext sfr page 0x00 automatically pushed on stack in sfrpage on spi0 interrupt
rev. 1.1 93 c8051f54x figure 12.4. sfr page stack upon pca interrupt occurring during a spi0 isr on exit from the pca interrupt servic e routine, the cip-51 will return to the spi0 isr. on execution of the reti instruction, sfr page 0x00 used to access the pca registers w ill be automatically popped off of the sfr page stack, and the contents of the sfrnext re gister will be moved to the sfrpage register. soft- ware in the spi0 isr can co ntinue to access sfrs as it did prior to the pca interrupt. likewise, the con- tents of sfrlast are moved to the sfrnext register. recall this was the sfr page value 0x0f being used to access smb0adr before the spi0 interrupt occurred. see figure 12.5. 0x00 (pca0) 0x00 (spi0) 0x0f (smb0adr) sfrpage sfrlast sfrnext sfr page 0x00 automatically pushed on stack in sfrpage on pca interrupt sfrpage pushed to sfrnext sfrnext pushed to sfrlast
c8051f54x 94 rev. 1.1 figure 12.5. sfr page stack upon return from pca interrupt on the execution of the re ti instruction in the spi0 isr, the valu e in sfrpage register is overwritten with the contents of sfrnext. the cip-51 may now acce ss the smb0adr register as it did prior to the interrupts occurring. see figure 12.6. 0x00 (spi0) 0x0f (smb0adr) sfrpage sfrlast sfrnext sfr page 0x00 automatically popped off of the stack on return from interrupt sfrnext popped to sfrpage sfrlast popped to sfrnext
rev. 1.1 95 c8051f54x figure 12.6. sfr page stack upon return from spi0 interrupt in the example above, all three bytes in the sfr page stack are accessible via the sfrpage, sfrnext, and sfrlast special function registers. if the stack is altered while servicing an in terrupt, it is possible to return to a different sfr page upon interrupt exit than selected prior to the interrupt call. direct access to the sfr page stack can be useful to enable real-t ime operating systems to control and manage context switching between multiple tasks. push operations on the sfr page stack only occur on interrupt service, and pop operations only occur on interrupt exit (execution on the reti instruction). the automatic switching of the sfrpage and operation of the sfr page stack as described above can be disabled in software by clearing the sfr automatic page enable bit (sfrpgen) in t he sfr page control register (sfr0cn). see sfr definition 12.1. 0x0f (smb0adr) sfrpage sfrlast sfrnext sfr page 0x00 automatically popped off of the stack on return from interrupt sfrnext popped to sfrpage
c8051f54x 96 rev. 1.1 sfr address = 0x84 ; sfr page = 0x0f sfr definition 12.1. sfr0cn: sfr page control bit 7 6 5 4 3 2 1 0 name sfrpgen type r r r r r r r r/w reset 0 0 0 0 0 0 0 1 bit name function 7:1 unused read = 0000000b; write = don?t care 0 sfrpgen sfr automatic page control enable. upon interrupt, the c8051 core will vector to the specified interr upt service routine and automatically switch the sfr page to the corresponding peripheral or function?s sfr page. this bit is used to control this autopaging function. 0: sfr automatic paging disa bled. the c8051 core will no t automatically change to the appropriate sfr page (i.e., the sfr page that contains the sfrs for the periph- eral/function that was the source of the interrupt). 1: sfr automatic paging enabled. upon interrupt, the c80 51 will switch the sfr page to the page that contains the sfrs fo r the peripheral or function that is the source of the interrupt.
rev. 1.1 97 c8051f54x sfr address = 0xa7 ; sfr page = all pages sfr definition 12.2. sfrpage: sfr page bit 7 6 5 4 3 2 1 0 name sfrpage[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sfrpage[7:0] sfr page bits. represents the sfr page the c8051 core uses when reading or modifying sfrs. write: sets the sfr page. read: byte is the sfr page the c8051 core is using. when enabled in the sfr page control register (sfr0cn), the c8051 core will automatically switch to the sfr page that contains the sfrs of the correspond- ing peripheral/function that caused the interrupt, and return to the previous sfr page upon return from interrupt (unless sfr stack was altered before a return- ing from the interrupt). sfrpage is th e top byte of the sfr page stack, and push/pop events of this stack are caused by interrupts (and not by reading/writ- ing to the sfrpage register)
c8051f54x 98 rev. 1.1 sfr address = 0x85 ; sfr page = all pages sfr definition 12.3. sfrnext: sfr next bit 7 6 5 4 3 2 1 0 name sfrnext[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sfrnext[7:0] sfr page bits. this is the value that will go to the sfr pa ge register upon a return fr om inter- rupt. write: sets the sfr page contained in th e second byte of the sfr stack. this will cause the sfrpage sfr to have this sfr page value upon a return from interrupt. read: returns the value of the sfr page contained in the second byte of the sfr stack. sfr page context is retained upon interrupts/return from interrupts in a 3 byte sfr page stack: sfrpage is the firs t entry, sfrnext is the second, and sfrlast is the third entry. the sfr stack bytes may be used alter the context in the sfr page stack, and will not caus e the stack to ?push? or ?pop?. only interrupts and return from interrupts cause pushes and pops of the sfr page stack.
rev. 1.1 99 c8051f54x sfr address = 0xa7 ; sfr page = all pages sfr definition 12.4. sfrlast: sfr last bit 7 6 5 4 3 2 1 0 name sfrlast[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sfrlast[7:0] sfr page stack bits. this is the value that will go to the sfrn ext register upon a return fr om inter- rupt. write: sets the sfr page in the last en try of the sfr stack. this will cause the sfrnext sfr to have this sfr page va lue upon a return from interrupt. read: returns the value of the sfr page contained in the last entry of the sfr stack. sfr page context is retained upon interrupts/return from interrupts in a 3 byte sfr page stack: sfrpage is the firs t entry, sfrnext is the second, and sfrlast is the third entry. the sfr stack bytes may be used alter the context in the sfr page stack, and will not caus e the stack to ?push? or ?pop?. only interrupts and return from interrupts cause pushes and pops of the sfr page stack.
c8051f54x 100 rev. 1.1 table 12.1. special function register (sfr) memory map for pages 0x0 and 0xf address page 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) f8 0 f spi0cn pca0l sn0 pca0h sn1 pca0cpl0 sn2 pca0cph0 sn3 pcacpl4 pcacph4 vdm0cn f0 0 f b (all pages) p0mat p0mdin p0mask p1mdin p1mat p2mdin p1mask p3mdin eip1 eip1 eip2 eip2 e8 0 f adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 pca0cpl3 pca0cpl3 rstsrc e0 0 f acc (all pages) xbr0 xbr1 cch0cn it01cf eie1 (all pages) eie2 (all pages) d8 0 f pca0cn pca0md pca0pwm pca0cpm0 pca0cpm1 pca0cpm2 pca0cpm3 pca0cpm4 pca0cpm5 d0 0 f psw (all pages) ref0cn lin0data lin0addr p0skip p1skip p2skip p3skip c8 0 f tmr2cn reg0cn lin0cf tmr2rll tmr2rlh tmr2l tmr2h pca0cpl5 pca0cph5 c0 0 f smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth xbr2 b8 0 f ip (all pages) adc0tk adc0mx adc0cf adc0l adc0h b0 0 f p3 (all pages) p2mat p2mask flscl (all pages) flkey (all pages) a8 0 f ie (all pages) smod0 emi0cn sbcon0 sbrll0 sbrlh0 p3mat p3mdout p3mask a0 0 f p2 (all pages) spi0cfg oscicn spi0ckr oscicrs spi0dat p0mdout p1mdout p2mdout sfrpage (all pages) 98 0 f scon0 sbuf0 cpt0cn cpt0md cpt0mx cpt1cn cpt1md oscifin cpt1mx oscxcn 90 0 f p1 (all pages) tmr3cn tmr3rll tmr3rlh tmr3l tmr3h clkmul 88 0 f tcon (all pages) tmod (all pages) tl0 (all pages) tl1 (all pages) th0 (all pages) th1 (all pages) ckcon (all pages) psctl clksel 80 0 f p0 (all pages) sp (all pages) dpl (all pages) dph (all pages) sfr0cn sfrnext (all pages) sfrlast (all pages) pcon (all pages) 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable)
rev. 1.1 101 c8051f54x table 12.2. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page acc 0xe0 accumulator 82 adc0cf 0xbc adc0 configuration 40 adc0cn 0xe8 adc0 control 42 adc0gth 0xc4 adc0 greater-than compare high 44 adc0gtl 0xc3 adc0 greater-than compare low 44 adc0h 0xbe adc0 high 41 adc0l 0xbd adc0 low 41 adc0lth 0xc6 adc0 less-than compare word high 45 adc0ltl 0xc5 adc0 less-than compare word low 45 adc0mx 0xbb adc0 mux configuration 59 adc0tk 0xba adc0 tracking mode select 43 b 0xf0 b register 82 cch0cn 0xe3 cache control 125 ckcon 0x8e clock control 228 clkmul 0x97 clock multiplier 141 clksel 0x8f clock select 136 cpt0cn 0x9a comparator0 control 65 cpt0md 0x9b comparator0 mode selection 66 cpt0mx 0x9c comparator0 mux selection 70 cpt1cn 0x9d comparator1 control 65 cpt1md 0x9e comparator1 mode selection 66 cpt1mx 0x9f comparator1 mux selection 70 dph 0x83 data pointer high 81 dpl 0x82 data pointer low 81 eie1 0xe6 extended interrupt enable 1 111 eie2 0xe7 extended interrupt enable 2 111 eip1 0xf6 extended interrupt priority 1 112 eip2 0xf7 extended interrupt priority 2 113 emi0cn 0xaa external memory interface control 88 flkey 0xb7 flash lock and key 123 flscl 0xb6 flash scale 124 ie 0xa8 interrupt enable 109 ip 0xb8 interrupt priority 110 it01cf 0xe4 int0/int1 configuration 116 lin0adr 0xd3 lin0 address 177
c8051f54x 102 rev. 1.1 lin0cf 0xc9 lin0 configuration 177 lin0dat 0xd2 lin0 data 178 oscicn 0xa1 internal oscillator control 138 oscicrs 0xa2 internal oscillator coarse control 139 oscifin 0x9e internal oscillator fine calibration 139 oscxcn 0x9f external oscillator control 143 p0 0x80 port 0 latch 161 p0mask 0xf2 port 0 mask configuration 157 p0mat 0xf1 port 0 match configuration 157 p0mdin 0xf1 port 0 input mode configuration 162 p0mdout 0xa4 port 0 output mode configuration 162 p0skip 0xd4 port 0 skip 163 p1 0x90 port 1 latch 163 p1mask 0xf4 port 1 mask configuration 158 p1mat 0xf3 port 1 match configuration 158 p1mdin 0xf2 port 1 input mode configuration 164 p1mdout 0xa5 port 1 output mode configuration 164 p1skip 0xd5 port 1 skip 165 p2 0xa0 port 2 latch 165 p2mask 0xb2 port 2 mask configuration 159 p2mat 0xb1 port 2 match configuration 159 p2mdin 0xf3 port 2 input mode configuration 166 p2mdout 0xa6 port 2 output mode configuration 166 p2skip 0xd6 port 2 skip 167 p3 0xb0 port 3 latch 167 p3mask 0xaf port 3 mask configuration 160 p3mat 0xae port 3 match configuration 160 p3mdin 0xf4 port 3 input mode configuration 168 p3mdout 0xae port 3 output mode configuration 168 p3skip 0xd7 port 3 skip 169 pca0cn 0xd8 pca control 263 pca0cph0 0xfc pca capture 0 high 268 pca0cph1 0xea pca capture 1 high 268 pca0cph2 0xec pca capture 2 high 268 pca0cph3 0xee pca capture 3 high 268 pca0cph4 0xfe pca capture 4 high 268 table 12.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
rev. 1.1 103 c8051f54x pca0cph5 0xcf pca capture 5 high 268 pca0cpl0 0xfb pca capture 0 low 268 pca0cpl1 0xe9 pca capture 1 low 268 pca0cpl2 0xeb pca capture 2 low 268 pca0cpl3 0xed pca capture 3 low 268 pca0cpl4 0xfd pca capture 4 low 268 pca0cpl5 0xce pca capture 5 low 268 pca0cpm0 0xda pca module 0 mode register 266 pca0cpm1 0xdb pca module 1 mode register 266 pca0cpm2 0xdc pca module 2 mode register 266 pca0cpm3 0xdd pca module 3 mode register 266 pca0cpm4 0xde pca module 4 mode register 266 pca0cpm5 0xdf pca module 5 mode register 266 pca0h 0xfa pca counter high 267 pca0l 0xf9 pca counter low 267 pca0md 0xd9 pca mode 264 pca0pwm 0xd9 pca pwm configuration 265 pcon 0x87 power control 128 psctl 0x8f program store r/w control 122 psw 0xd0 program status word 83 ref0cn 0xd1 voltage reference control 62 reg0cn 0xc9 voltage regulator control 73 rstsrc 0xef reset source configuration/status 134 sbcon0 0xab uart0 baud rate generator control 212 sbrlh0 0xad uart0 baud rate reload high byte 213 sbrll0 0xac uart0 baud rate reload low byte 213 sbuf0 0x99 uart0 data buffer 212 scon0 0x98 uart0 control 210 sfr0cn 0x84 sfr page control 96 sfrlast 0x86 sfr stack last page 99 sfrnext 0x85 sfr stack next page 98 sfrpage 0xa7 sfr page select 97 smb0cf 0xc1 smbus0 configuration 193 smb0cn 0xc0 smbus0 control 195 smb0dat 0xc2 smbus0 data 197 smod0 0xa9 uart0 mode 211 table 12.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
c8051f54x 104 rev. 1.1 sn0 0xf9 serial number 0 84 sn1 0xfa serial number 1 84 sn2 0xfb serial number 2 84 sn3 0xfc serial number 3 84 sp 0x81 stack pointer 82 spi0cfg 0xa1 spi0 configuration 221 spi0ckr 0xa2 spi0 clock rate control 223 spi0cn 0xf8 spi0 control 222 spi0dat 0xa3 spi0 data 223 tcon 0x88 timer/counter control 233 th0 0x8c timer/counter 0 high 236 th1 0x8d timer/counter 1 high 236 tl0 0x8a timer/counter 0 low 235 tl1 0x8b timer/counter 1 low 235 tmod 0x89 timer/counter mode 234 tmr2cn 0xc8 timer/counter 2 control 240 tmr2h 0xcd timer/counter 2 high 242 tmr2l 0xcc timer/counter 2 low 242 tmr2rlh 0xcb timer/counter 2 reload high 241 tmr2rll 0xca timer/counter 2 reload low 241 tmr3cn 0x91 timer/counter 3 control 246 tmr3h 0x95 timer/counter 3 high 248 tmr3l 0x94 timer/counter 3 low 248 tmr3rlh 0x93 timer/counter 3 reload high 247 tmr3rll 0x92 timer/counter 3 reload low 247 vdm0cn 0xff v dd monitor control 132 xbr0 0xe1 port i/o crossbar control 0 154 xbr1 0xe2 port i/o crossbar control 1 155 xbr2 0xc7 port i/o crossbar control 2 156 table 12.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
rev. 1.1 105 c8051f54x 13. interrupts the c8051f54x devices include an extended interrupt system supporting a total of 14 interrupt sources with two priority levels. the allocati on of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. each interrupt source has one or more associ- ated interrupt-pending flag(s) located in an sfr. when a peripheral or external source meets a valid inter- rupt condition, the associated interr upt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede- termined address to begin execution of an interrupt se rvice routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (t he interrupt-pending flag is set to logic 1 regard- less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie, eie1, or ei e2). however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. note: any instruction that clears a bit to disable an interrupt should be immediately followed by an instruction that has two or more opcode bytes. using ea (global interrupt enable) as an example: // in 'c': ? ea = 0; // clear ea bit. ? ea = 0; // this is a dummy instruction with two-byte opcode. ? ; in assembly: ? clr ea ; clear ea bit. ? clr ea ; this is a dummy instruction with two-byte opcode. for example, if an interrupt is posted during the exec ution phase of a "clr ea" opcode (or any instruction which clears a bit to disable an interrupt source), an d the instruction is followed by a single-cycle instruc- tion, the interrupt may be taken. howeve r, a read of the enable bit will retu rn a 0 inside the interrupt service routine. when the bit-clea ring opcode is followed by a multi-cycle instruction, th e interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of the next instruction. 13.1. mcu interrupt sources and vectors the c8051f54x mcus support 17 interrupt sources. software can simulate an interrupt by setting any interrupt-pending flag to lo gic 1. if interrupts are ena bled for the flag, an interr upt request will be generated and the cpu will vector to the isr address associated wit h the interrupt- pending flag. mcu interrupt sources, associated vector addresses, priority order and control bits are summarized in table 13.1. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and t he behavior of its interrupt-pending flag(s).
c8051f54x 106 rev. 1.1 13.1.1. interr upt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior- ity interrupt service routine can be pree mpted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ie, eip1, or eip2) used to configure its priority level. low priority is the default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if bo th interrupts have the same pr iority level, a fixed prior- ity order is used to arbitrate, given in table 13.1. 13.1.2. interr upt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 5 system clock cycles: 1 clock cycle to detect the interr upt and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new in terrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the in terrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycl es to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction.
rev. 1.1 107 c8051f54x table 13.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none n/a n/a always enabled always highest external interrupt 0 ( int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 ( int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) ? wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6) pspi0 (ip.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1.0) adc0 window com - pare 0x0043 8 ad0wint (adc0cn.3) y n ewadc0 (eie1.1) pwadc0 (eip1.1) adc0 conversion complete 0x004b 9 ad0int (adc0cn.5) y n eadc0 (eie1.2) padc0 (eip1.2) programmable counter array 0x0053 10 cf (pca0cn.7) ccfn (pca0cn.n) covf (pca0pwm.6) y n epca0 (eie1.3) ppca0 (eip1.3) comparator0 0x005b 11 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) n n ecp0 (eie1.4) pcp0 (eip1.4) comparator1 0x0063 12 cp1fif (cpt1cn.4) cp1rif (cpt1cn.5) n n ecp1 (eie1.5) pcp1 (eip1.5) timer 3 overflow 0x006b 13 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.6) pt3 (eip1.6) lin0 0x0073 14 lin0int (linst.3) n n* elin0 (eie1.7) plin0 (eip1.7) voltage regulator dropout 0x007b 15 n/a n/a n/a ereg0 (eie2.0) preg0 (eip2.0) port match 0x008b 17 none n/a n/a emat (eie2.2) pmat (eip2.2) *note: the lin0int bit is cleared by setting rstint (linctrl.3)
c8051f54x 108 rev. 1.1 13.2. interrupt re gister descriptions the sfrs used to enable the interrupt sources and set their priority level are described in this section. refer to the data sheet section associated with a pa rticular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
rev. 1.1 109 c8051f54x sfr address = 0xa8; bit-addressable; sfr page = all pages sfr definition 13.1. ie: interrupt enable bit 7 6 5 4 3 2 1 0 name ea espi0 et2 es0 et1 ex1 et0 ex0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ea enable all interrupts. globally enables/disables all interrupts. it ov errides individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. 6 espi0 enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5 et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. 3 et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 1 et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. 0 ex0 enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input.
c8051f54x 110 rev. 1.1 sfr address = 0xb8; bit-addressable; sfr page = all pages sfr definition 13.2. ip: interrupt priority bit 7 6 5 4 3 2 1 0 name pspi0 pt2 ps0 pt1 px1 pt0 px0 type r r/w r/w r/w r/w r/w r/w r/w reset 1 0 0 0 0 0 0 0 bit name function 7 unused read = 1b, write = don't care. 6 pspi0 serial peripheral interface (spi 0) interrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5 pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. 3 pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 se t to low priority level. 1: external interrupt 1 se t to high priority level. 1 pt0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 se t to low priority level. 1: external interrupt 0 se t to high priority level.
rev. 1.1 111 c8051f54x sfr address = 0xe6; sfr page = all pages sfr definition 13.3. eie1: extended interrupt enable 1 bit 7 6 5 4 3 2 1 0 name elin0 et3 ecp1 ecp0 epca0 eadc0 ewadc0 esmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 elin0 enable lin0 interrupt. this bit sets the masking of the lin0 interrupt. 0: disable lin0 interrupts. 1: enable interrupt requests generated by the lin0int flag. 6 et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. 5 ecp1 enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1rif or cp1fif flags. 4 ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. 3 epca0 enable programmable counte r array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. 2 eadc0 enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversi on complete interrupt. 1: enable interrupt requests generated by the ad0int flag. 1 ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (ad0wint). 0 esmb0 enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0.
c8051f54x 112 rev. 1.1 sfr address = 0xf6; sfr page = 0x00 and 0x0f sfr definition 13.4. eip1: extended interrupt priority 1 bit 7 6 5 4 3 2 1 0 name plin0 pt3 pcp1 pcp0 ppca0 padc0 pwadc0 psmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 plin0 lin0 interrupt priority control. this bit sets the priority of the lin0 interrupt. 0: lin0 interrupts set to low priority level. 1: lin0 interrupts set to high priority level. 6 pt3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts set to low priority level. 1: timer 3 interrupts set to high priority level. 5 pcp1 comparator0 (cp1) interru pt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. 4 pcp0 comparator0 (cp0) interru pt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 3 ppca0 programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 2 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete interrupt set to high priority level. 1 pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt se t to low priority level. 1: adc0 window interrupt set to high priority level. 0 psmb0 smbus (smb0) interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level.
rev. 1.1 113 c8051f54x sfr address = 0xe7; sfr page = all pages sfr definition 13.5. eie2: extended interrupt enable 2 bit 7 6 5 4 3 2 1 0 name emat ereg0 type r r r r r r/w r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:3 unused read = 00000b; write = don?t care. 2 emat enable port match interrupt. this bit sets the masking of the port match interrupt. 0: disable all port match interrupts. 1: enable interrupt requests generated by a port match 1 unused read = 0b; write = don?t care. 0 ereg0 enable voltage regulator dropout interrupt. this bit sets the masking of the voltage regulator dropout interrupt. 0: disable the voltage regulator dropout interrupt. 1: enable the voltage regulator dropout interrupt.
c8051f54x 114 rev. 1.1 sfr address = 0xf7; sfr page = 0x00 and 0x0f sfr definition 13.6. eip2: extended interrupt priority enabled 2 bit 7 6 5 4 3 2 1 0 name pmat preg0 type r r r r r r/w r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:3 unused read = 00000b; write = don?t care. 2 pmat port match interrupt priority control. this bit sets the priority of the port match interrupt. 0: port match interrupt se t to low priority level. 1: port match interrupt se t to high priority level. 1 unused read = 0b; write = don?t care. 0 preg0 voltage regulator dropout interrupt priority control. this bit sets the priority of the voltage regulator dropout interrupt. 0: voltage regulator dropout inte rrupt set to low priority level. 1: voltage regulator dropout interrupt set to high priority level.
rev. 1.1 115 c8051f54x 13.3. external interrupts int0 and int1 the int0 and int1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. the in0pl (int0 polarity) and in1pl (int1 polarity) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon (section ?23.1. timer 0 and timer 1? on page 229) select level or edge sensitive. the table below lis ts the possible configurations. int0 and int1 are assigned to port pins as defined in the it01cf register (see sfr definition 13.7). note that int0 and int0 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins wit hout disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section ?18.3. priority crossbar decoder? on page 150 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flags for the int0 and int1 external inter- rupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu ve ctors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); th e flag remains logic 0 while the input is inactive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt request befor e execution of the isr completes or another interrup t request will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 1 0 active low, edge sensitive 1 0 active low, edge sensitive 1 1 active high, edge sensitive 1 1 a ctive high, edge sensitive 0 0 active low, level sensitive 0 0 active low, level sensitive 0 1 active high, level sensitive 0 1 active high, level sensitive
c8051f54x 116 rev. 1.1 sfr address = 0xe4; sfr page = 0x0f sfr definition 13.7. it01cf: int0/int1 configuration bit 7 6 5 4 3 2 1 0 name in1pl in1sl[2:0] in0pl in0sl[2:0] type r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 in1pl int1 polarity. 0: int1 input is active low. 1: int1 input is active high. 6:4 in1sl[2:0] int1 port pin se lection bits. these bits select which port pin is assigned to int1 . note that this pin assignment is independent of the crossbar; int1 will monitor the assigned port pin without disturb - ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p1.0 001: select p1.1 010: select p1.2 011: select p1.3 100: select p1.4 101: select p1.5 110: select p1.6 111: select p1.7 3 in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high. 2:0 in0sl[2:0] int0 port pin se lection bits. these bits select which port pin is assigned to int0 . note that this pin assignment is independent of the crossbar; int0 will monitor the assigned port pin without disturb - ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p1.0 001: select p1.1 010: select p1.2 011: select p1.3 100: select p1.4 101: select p1.5 110: select p1.6 111: select p1.7
rev. 1.1 117 c8051f54x 14. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system, a single byte at a time, through the c2 interface or by soft- ware using the movx instruct ion. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automatically timed by hardware for proper execut ion; data polling to determine the end of the write/erase oper ation is not required. code execution is stalled during a flash write/erase oper- ation. refer to table 6.5 for complete flash memory electrical characteristics. 14.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial- ized device. for details on the c2 commands to program flash memory, see section ?25. c2 interface? on page 269. to ensure the integrity of flas h contents, it is strongly recommended that the on-chip v dd monitor be enabled in any system that includes code that writes and/or erases flash memory from software. see sec- tion 14.4 for more details. before performing any fl ash write or erase procedure, set the flewt bit in flash scale register (flscl) to ?1?. also, note that 8-bit movx instructions cannot be used to erase or write to flash memory at addresses higher than 0x00ff 14.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. th e flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per- formed. the flkey register is det ailed in sfr definition 14.2. 14.1.2. flash erase procedure the flash memory can be programmed by software using the movx write instru ction with the address and data byte to be programmed provided as normal ope rands. before writing to flash memory using movx, flash write operations must be enabled by doing t he following: (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target flash memory); and (2) writing the flash key codes in sequence to the flash lock regi ster (flkey). the pswe bit remains set un til cleared by software. a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. the flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: 1. disable interrupts (recommended). 2. set the psee bit (register psctl). 3. set the pswe bit (register psctl). 4. write the first key code to flkey: 0xa5. 5. write the second key code to flkey: 0xf1. 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. 7. clear the pswe and psee bits.
c8051f54x 118 rev. 1.1 14.1.3. flash write procedure flash bytes are programmed by software with the following sequence: 1. disable interrupts (recommended). 2. erase the 512-byte flash page containing the ta rget location, as described in section 14.1.2. 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. write the first key code to flkey: 0xa5. 6. write the second key code to flkey: 0xf1. 7. using the movx instruction, write a single data byte to the desired location within the 512-byte sector. 8. clear the pswe bit. steps 5?7 must be repeated for each byte to be written. after flash writes are complete, pswe should be cleared so that movx instructions do not target program memory. 14.1.4. flash write optimization the flash write procedure includes a block write opti on to optimize the time to perform consecutive byte writes. when block write is enabled by setting the chblkw bit ( cch0cn.0), writes to two consecutive bytes in flash require the same amount of time as a si ngle byte write. this is performed by caching the first byte that is written to flash and then committing both bytes to flash when the second byte is written. when block writes are enabled, if the second write does not occur, the first data byte written is not actually written to flash. flash bytes with block write enabled are programmed by software with the following sequence: 1. disable interrupts (recommended). 2. erase the 512-byte flash page containing the ta rget location, as described in section 14.1.2. 3. set the chblkw bit (register cch0cn). 4. set the pswe bit (register psctl). 5. clear the psee bit (register psctl). 6. write the first key code to flkey: 0xa5. 7. write the second key code to flkey: 0xf1. 8. using the movx instruction, write th e first data byte to the desired location within the 512-byte sector. 9. write the first key code to flkey: 0xa5. 10.write the second key code to flkey: 0xf1. 11. using the movx instruction, write the second data byte to the desired location within the 512-byte sector. the location of the second byte must be t he next higher address from the first data byte. 12.clear the pswe bit. 13.clear the chblkw bit.
rev. 1.1 119 c8051f54x 14.2. non-volati le data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instructi on. note: movx read instructions always target xram. 14.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. the program store write enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to 1 before software can modify the flash memory; both pswe and psee must be set to 1 before soft- ware can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, or erases) by unpr otected code or the c2 inte rface. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x01ff), where n is the ones complement number represented by the security lock byte. note that the page containing the flash security lock byte is unlocked when no other flash pages are locked (all bits of the lock byte are 1) and locked when any other flash pages are locked (any bit of the lock byte is 0). see example in figure 14.1. figure 14.1. flash program memory map lock byte page locked flash pages access limit set according to the flash security lock byte lock byte reserved area unlocked flash pages locked when any other flash pages are locked security lock byte: 11111101b 1s complement: 00000010b flash pages locked: 3 (first two flash pages + lock byte page)
c8051f54x 120 rev. 1.1 the level of flash security depends on the flash ac cess method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. table 14.1 summarizes the flash security features of the c8051f54x devices. table 14.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages (except page with lock byte) permitted permitted permitted read, write or erase locked pages (except page with lock byte) not permitted flash error reset permitted read or write page containing lock byte (if no pages are locked) permitted permitted permitted read or write page containing lock byte (if any page is locked) not permitted flash error reset permitted read contents of lock byte (if no pages are locked) permitted permitted permitted read contents of lock byte (if any page is locked) not permitted flash error reset permitted erase page containing lock byte (if no pages are locked) permitted flash error reset flash error reset erase page containing lock byte?unlock all pages (if any page is locked) c2 device erase only flash error reset flash error reset lock additional pages (change 1s to 0s in the lock byte) not permitted flash error reset flash error reset unlock individual pages (change 0s to 1s in the lock byte) not permitted flash error reset flash error reset read, write or erase reserved area not permitted see note see note note: flash reads will return indeterminate data . flash writes and erases are ignored. ? c2 device erase?erases all flash pages in cluding the page containing the lock byte. flash error reset?not permitted; ca uses flash error device reset (ferror bit in rstsrc is 1 after reset). - all prohibited operations that are performed via the c2 interface are ignored (do not cause device reset). - locking any flash page also locks th e page containing the lock byte. - once written to, the lock byte cannot be modifi ed except by performing a c2 device erase. - if user code writes to the lock byte, the lock does not take effect until the next device reset.
rev. 1.1 121 c8051f54x 14.4. flash write and erase guidelines any system which contains routines which write or er ase flash memory from software involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of v dd , system clock frequency, or temperature. this accidental execution of flash modi- fying code can result in alteration of flash memory contents causing a system failure that is only recover- able by re-flashing the code in the device. the following guidelines are recommended for any syst em which contains routin es which write or erase flash from code. 14.4.1. v dd maintenance and the v dd monitor 1. if the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. enable the on-chip v dd monitor and enable the v dd monitor as a reset source as early in code as possible. this should be the first set of instructio ns executed after the reset vector. for c-based systems, this will involve modifyin g the startup code a dded by the c compiler. see your compiler documentation for more details. make certain that th ere are no delays in software between enabling the v dd monitor and enabling the v dd monitor as a reset source. code examples showing this can be found in ?an201: writing to flash from firmware", available from th e silicon laboratories web site. 3. as an added precaution, explicitly enable the v dd monitor and enable the v dd monitor as a reset source inside the functions that write and erase flash memory. the v dd monitor enable instructions should be placed just after the in struction to set pswe to a 1, but before the flash write or erase operation instruction. 4. make certain that all writes to the rstsrc (reset sources) register use di rect assignment operators and explicitly do not use the bit-wise operators (such as and or or). for example, "rstsrc = 0x02" is correct. "rstsrc |= 0x02" is incorrect. 5. make certain that all writes to the rstsrc register explicitly set the porsf bi t to a 1. areas to check are initialization code which enab les other reset sources, such as the missing clock detector or comparator, for example, and instructions which force a software reset. a global search on "rstsrc" can quickly verify this. 14.4.2. pswe maintenance 1. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a 1. there should be exactly one routine in code that sets pswe to a 1 to write flash bytes and one routine in code that sets pswe and psee both to a 1 to erase flash pages. 2. minimize the number of variable accesses while pswe is set to a 1. handle pointer address updates and loop variable maintenance outside the "pswe = 1;... pswe = 0;" area. code examples showing this can be found in ?an201: writing to flash from firmware" available from the silicon laboratories web site. 3. disable interrupts prior to setting pswe to a 1 and leave them disabled until after pswe has been reset to '0'. any interrupt s posted during the flash write or eras e operation will be serviced in priority order after the flash operation has been completed a nd interrupts have been re-enabled by software. 4. make certain that the flash write and erase poin ter variables are not located in xram. see your compiler documentation for instructions regarding how to explicitly locate variab les in different memory areas. 5. add address bounds checking to th e routines that write or erase flas h memory to ensure that a routine called with an illegal address does not result in modification of the flash.
c8051f54x 122 rev. 1.1 14.4.3. system clock 1. if operating from an external crystal, be advised th at crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noisy environment, use the internal oscillator or use an external cmos clock. 2. if operating from the external oscillator, switch to the internal oscillator du ring flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after the flash operation has completed. additional flash recommendations and example code ca n be found in ?an201: writing to flash from firm- ware" available from the s ilicon laboratories web site. sfr address = 0x8f; sfr page = 0x00 sfr definition 14.1. psctl: program store r/w control bit 7 6 5 4 3 2 1 0 name psee pswe type r r r r r r r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:2 unused read = 000000b, write = don?t care. 1 psee program store erase enable. setting this bit (in combination with pswe) allows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruction will erase the entire page that contains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0 pswe program store write enable. setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabl ed; the movx write instruction targets flash memory.
rev. 1.1 123 c8051f54x sfr address = 0xb7; sfr page = all pages sfr definition 14.2. flkey: flash lock and key bit 7 6 5 4 3 2 1 0 name flkey[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 flkey[7:0] flash lock and key register. write: this register provides a lock and key func tion for flash erasures and writes. flash writes and erases ar e enabled by writing 0xa5 follo wed by 0xf1 to the flkey regis - ter. flash writes and erases are automatically disabled after the next write or erase is complete. if any writes to flkey are performed incorrectly, or if a flash write or erase operation is attempted while these operations are disa bled, the flash will be perma - nently locked from writes or erasures unt il the next device reset. if an application never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset.
c8051f54x 124 rev. 1.1 sfr address = 0xb6; sfr page = all pages sfr definition 14.3. flscl: flash scale bit 7 6 5 4 3 2 1 0 name reserved reserved reserved flrt reserved reserved flewt reserved type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:5 reserved must write 000b. 4 flrt flash read time control. this bit should be programmed to the smalle st allowed value, according to the system clock speed. 0: sysclk < 25 mhz (flash read stro be is one system clock). 1: sysclk > 25 mhz (flash read strobe is two system clocks). 3:2 reserved must write 00b. 1 flewt flash erase write time control. this bit should be set to 1b before writing or erasing flash. 0: short flash erase / write timing. 1: extended flash erase / write timing. 0 reserved must write 0b.
rev. 1.1 125 c8051f54x sfr address = 0xe3; sfr page = 0x0f sfr address = 0xbe; sfr page = 0x0f sfr definition 14.4. cch0cn: cache control bit 7 6 5 4 3 2 1 0 name reserved reserved chpfen reserved reserved reserved reserved chblkw type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 0 0 0 0 0 bit name function 7:6 reserved must write 00b 5 chpfen cache prefect enable bit. 0: prefetch engine is disabled. 1: prefetch engine is enabled. 4:1 reserved must write 0000b. 0 chblkw block write enable bit. this bit allows block writes to flash memory from firmware. 0: each byte of a software flas h write is written individually. 1: flash bytes are written in groups of two. sfr definition 14.5. oneshot: flash oneshot period bit 7 6 5 4 3 2 1 0 name period[3:0] type r r r r r/w r/w r/w r/w reset 0 0 0 0 1 1 1 1 bit name function 7:4 unused read = 0000b. write = don?t care. 3:0 period[3:0] oneshot period control bits. these bits limit the internal flash read st robe width as follows. when the flash read strobe is de-asserted, the flash memory enters a low-power state for the remainder of the system clock cycle. flash rdmax 5 ns period 5 ns ? ?? + =
c8051f54x 126 rev. 1.1 15. power management modes the c8051f54x devices have three software programmable power management modes: idle, stop, and suspend. idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is an enhanced power-saving mode implemented by the high-speed os cillator peripheral. idle mode halts the cpu while leavin g the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock de tector) are inactive, and th e internal oscillator is stopped (analog peripherals remain in their se lected states; the external o scillator is not affected). sus- pend mode is similar to stop mode in that the internal oscillator an d cpu are halted, but the device can wake on events such as a port match or comparator low output. since clocks are running in idle mode, power consumption is dependent upon the system clo ck frequency and the number of peripherals left in active mode before entering idle. stop mode and suspend mode consume the least power because the majority of the device is shut down with no clocks active. sfr definition 15.1 describes the power control register (pcon) used to control the c8051f54x devi ces? stop and idle power management modes. sus- pend mode is controlled by the suspend bit in the oscicn register (s fr definition 17.2). although the c8051f54x has idle, stop, and suspend modes available, more control over the device power can be achieved by enabling/disabling individ ual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw little power when they are not in use. turning off oscillators lowers power consumption considerably, at the expense of reduced functionality. 15.1. idle mode setting the idle mode select bit (pcon.0) causes the hardware to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: if the instructio n following the write of the idle bit is a sing le-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. therefore, instructi ons that set the idle bit should be followed by an instruction that has two or mo re opcode bytes, for example: // in ?c?: pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset a nd thereby termi- nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, th e wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro- vides the opportunity for additional power savings, allo wing the system to remain in the idle mode indefi- nitely, waiting for an external stimul us to wake up the system. refer to section ?16.6. pca watchdog timer reset? on page 133 for more information on the use a nd configuration of the wdt.
rev. 1.1 127 c8051f54x 15.2. stop mode setting the stop mode select bit (pcon.1) causes the co ntroller core to enter stop mode as soon as the instruction that sets the bit complete s execution. in stop mode the intern al oscillator, cpu, and all digital peripherals are stopp ed; the state of the external oscillator circ uit is not affected. ea ch analog peripheral (including the external oscillator circui t) may be shut down i ndividually prior to ente ring stop mode. stop mode can only be terminated by an internal or external reset. on reset, the device performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout of 100 s. 15.3. suspend mode setting the suspend bit (oscicn.5) causes the hardware to halt the cpu and the high-frequency inter- nal oscillator, and go into suspend m ode as soon as the inst ruction that sets the bit completes execution. all internal registers and memory main tain their original data. most digital peripherals are not active in sus- pend mode. the exception to th is is the port match feature. suspend mode can be terminated by three types of events, a port match (described in section ?18.5. port match? on page 157), a comparator low output (if enabled), or a device reset event. when suspend mode is terminated, the device will contin ue execution on the instruction fo llowing the one that set the suspend bit. if the wake event was configur ed to generate an inte rrupt, the interrupt will be serviced upon waking the device. if suspend mode is terminated by an inte rnal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: when entering suspend mode, firmware must se t the ztcen bit in ref0cn (sfr definition 7.1).
c8051f54x 128 rev. 1.1 sfr address = 0x87; sfr page = all pages sfr definition 15.1. pcon: power control bit 7 6 5 4 3 2 1 0 name gf[5:0] stop idle type r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:2 gf[5:0] general purpose flags 5?0. these are general purpose flags for use under software control. 1 stop stop mode select. setting this bit will place the cip-51 in st op mode. this bit will always be read as 0. 1: cpu goes into stop mode (internal oscillator stopped). 0 idle idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clo ck to cpu, but clock to timers, interrupts, serial ports, and analog peripherals are still active.)
rev. 1.1 129 c8051f54x 16. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur- ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter- nal oscillator. the watchdog timer is enabled with the system clock divided by 12 as its clock source. pro- gram execution begins at location 0x0000. figure 16.1. reset sources pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable errant flash operation /rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable
c8051f54x 130 rev. 1.1 16.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . a delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 16.2. plots the power-on and v dd monitor reset timing. on exit from a power-on reset, the porsf flag (rstsr c.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was t he cause of reset. the content of internal data mem- ory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. figure 16.2. power-on and v dd monitor reset timing 16.2. power-fail reset/v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 16.2). when v dd returns to a level above v rst , the cip-51 will be released from the reset st ate. note that even though internal data memory contents are not altered by the power-fa il reset, it is impossib le to determine if v dd dropped below the level required for data retenti on. if the porsf flag reads 1, the data may no longer be valid. the v dd monitor is enabled after power-on resets. its defined st ate (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled by code and a software reset is performed, the v dd monitor will still be disabled after the reset. to protect the integrity of flash contents, the v dd monitor must be enabled to the higher setting (vdmlvl = 1) and selected as a reset source if soft- ware contains routines which erase or write flash memory. if the v dd monitor is not enabled and set to the high level, any erase or write performed on flash memory will cause a flash error device reset. power-on reset vdd monitor reset /rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.55 v rst vdd
rev. 1.1 131 c8051f54x important note: if the v dd monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabled and stabi- lized may cause a system reset. in some applications, this reset may be undesirable. if this is not desirable in the application, a delay should be introduced betwe en enabling the monitor and selecting it as a reset source. the procedure for enabling the v dd monitor and configuring it as a reset source from a disabled state is as follows: 1. enable the v dd monitor (vdmen bit in vdm0cn = 1). 2. if necessary, wait for the v dd monitor to stabilize (see table 6.4 for the v dd monitor turn-on time). ? note: this delay should be omitted if software contains routines that erase or write flash memory. 3. select the v dd monitor as a reset source (porsf bit in rstsrc = 1). see figure 16.2 for v dd monitor timing; note that the power-on -reset delay is not incurred after a v dd monitor reset. see table 6.4 for complete electrical characteristics of the v dd monitor. note: the output of the internal voltage regulator is calibrated by the mcu immediately after any reset event. the output of the un-calibrated internal regulator could be below the high threshold setting of the vdd monitor. if this is the case and the v dd monitor is set to the high threshold setting and if the mcu receives a non-power on reset (por), the mcu w ill remain in reset until a por occurs (i.e., v dd monitor will keep the device in reset). a por will force the v dd monitor to the low threshold setting which is guaranteed to be below the un-calibrated output of the internal regulator. the device will then exit reset and resume normal operation. it is for this reason silicon labs strongly recommends that the v dd monitor is always left in the low threshold setting (i.e., default value upon por). when programming the flash in-system, the v dd monitor must be set to the high threshold setting. for the highest system reliability, the time the v dd monitor is set to the high threshold setting should be minimized (e.g., setting the v dd monitor to the high threshold setting just before the flash write operation and then changing it back to the low threshold settin g immediately after the flash write operation).
c8051f54x 132 rev. 1.1 sfr address = 0xff; sfr page = 0x00 16.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert- ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise- induced resets. see table 6.4 for complete rst pin spec- ifications. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 16.4. missing cl ock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the syst em clock. if the system clock remains high or low for more than the time specif ied in table 6.4, ?reset electrical characteristics,? on page 52, the one-shot will time out and generate a reset. afte r a mcd reset, the mcdrsf flag (rst- src.2) will read 1, signifying the mc d as the reset source; otherwise, th is bit reads 0. writing a 1 to the mcdrsf bit enables the missing clock detector; wr iting a 0 disables it. the state of the rst pin is unaf- fected by this reset. sfr definition 16.1. vdm0cn: v dd monitor control bit 7 6 5 4 3 2 1 0 name vdmen vddstat vdmlvl type r/w r r/w r r r r r reset varies varies 0 0 0 0 0 0 bit name function 7 vdmen v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate sys - tem resets until it is also selected as a reset source in register rstsrc ( sfr def - inition 16.2 ). selecting the v dd monitor as a reset source before it has stabilized may generate a system reset. in systems wher e this reset would be undesirable, a delay should be introduced between enabling the v dd monitor and selecting it as a reset source. see ta b l e 6.4 for the minimum v dd monitor turn-on time. 0: v dd monitor disabled. 1: v dd monitor enabled. 6 vddstat v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. 5 vdmlvl v dd monitor level select. 0: v dd monitor threshold is set to vrst-low 1: v dd monitor threshold is set to vrst-hig h. this setting is required for any sys - tem includes code that writes to and/or erases flash. 4:0 unused read = 00000b; write = don?t care.
rev. 1.1 133 c8051f54x 16.5. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0?), the device is put into the reset state. after a compar ator0 reset, the c0rsef flag (rst src.5) will read 1 signifying comparator0 as the reset source; otherwise, this bit reads 0. the state of the rst pin is unaffected by this reset. 16.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as desc ribed in section ?24.4. watchdog timer mode? on page 260; the wdt is enabled and clocked by syscl k/12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is generated and the wdtrsf bit (rstsrc.5) is set to 1. the state of the rst pin is unaffected by this reset. 16.7. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to 1 and a movx write operation targets an address in or above the reserved space. ? a flash read is attempted above user code space. this occurs when a movc operation targets an address in or above the reserved space. ? a program read is attempted above user code space. this occurs when user code attempts to branch to an address in or above the reserved space. ? a flash read, write or erase attempt is rest ricted due to a flash security setting (see section ?14.3. security options? on page 119 ). ? a flash read, write, or erase is attempted when the vdd monitor is not enabled to the high threshold and set as a reset source. the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset. 16.8. software reset software may force a reset by wr iting a 1 to the swrsf bit (rstsr c.4). the swrsf bit will read 1 fol- lowing a software forced reset. the state of the rst pin is unaffected by this reset.
c8051f54x 134 rev. 1.1 sfr address = 0xef; sfr page = 0x00 sfr definition 16.2. rstsrc: reset source bit 7 6 5 4 3 2 1 0 name ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf type r r r/w r/w r r/w r/w r reset 0 varies varies varies varies varies varies varies bit name description write read 7 unused unused. don?t care. 0 6 ferror flash error reset flag. n/a set to 1 if flash read/write/erase error caused the last reset. 5 c0rsef comparator0 reset enable and flag. writing a 1 enables comparator0 as a reset source (active-low). set to 1 if comparator0 caused the last reset. 4 swrsf software reset force and flag. writing a 1 forces a sys - tem reset. set to 1 if last reset was caused by a write to swrsf. 3 wdtrsf watchdog timer reset flag. n/a set to 1 if watchdog timer overflow caused the last reset. 2 mcdrsf missing clock detector enable and flag. writing a 1 enables the missing clock detector. the mcd triggers a reset if a missing clock condition is detected. set to 1 if missing clock detector timeout caused the last reset. 1 porsf power-on/v dd monitor reset flag, and v dd monitor reset enable. writing a 1 enables the v dd monitor as a reset source. writing 1 to this bit before the v dd monitor is enabled and stabilized may cause a system reset. set to 1 anytime a power- on or v dd monitor reset occurs. when set to 1 all other rstsrc flags are inde - terminate. 0 pinrsf hw pin reset flag. n/a set to 1 if rst pin caused the last reset. note: do not use read-modify-write operations on this register
rev. 1.1 135 c8051f54x 17. oscillators and clock selection c8051f54x devices include a programmable internal hi gh-frequency oscillator, an external oscillator drive circuit, and a clock multiplier. th e internal oscillator ca n be enabled/disabled an d calibrated using the oscicn, oscicrs, and oscifin registers, as shown in figure 17.1. the system clock can be sourced by the external oscillator ci rcuit or the internal oscillator. the cl ock multiplier can produce three possible base outputs which can be scaled by a programmable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7: internal oscillator x 2, external oscilla tor x 2, or external oscillator x 4. figure 17.1. oscillator options 17.1. system clock selection the clksl[1:0] bits in register cl ksel select which osc illator source is used as the system clock. clksl[1:0] must be set to 01b for the system clock to run from th e external oscillator; however the exter- nal oscillator may still clock certain per ipherals (timers, pca) when the inte rnal oscillator is selected as the system clock. the system clock may be switched on-the-fly be tween the inte rnal oscillator, external oscilla- tor, and clock multiplier so long as the selected clock source is enabled and has settled. the internal oscillator requir es little start-up time and may be selected as the system clock immediately fol- lowing the register write which enab les the oscillator. the external rc and c modes also typically require no startup time. external crystals and ceramic resonato rs however, typically require a start-up time before they are settled and ready for use. the crystal valid flag (xtlvld in register oscxcn) is set to 1 by hardware when the external crystal or cera mic resonator is settled. in crystal mode, to avoid reading a false xtlvld, soft- ware should delay at least 1 ms between enabling the external oscillator and checking xtlvld. osc programmable internal clock generator input circuit en sysclk n oscicrs oscicn ioscen1 ioscen0 ifcn1 ifcn0 xtal1 xtal2 option 2 vdd xtal2 option 1 10m ? option 3 xtal2 option 4 xtal2 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 oscifin clksel sel1 sel0 ifcn2 clkmul mulen mulinit mulrdy muldiv2 muldiv0 mulsel1 mulsel0 muldiv1 n x4 iosc/2 exosc exosc/2 iosc iosc exosc clock multiplier cal
c8051f54x 136 rev. 1.1 sfr address = 0x8f; sfr page = 0x0f; sfr definition 17.1. clksel: clock select bit 7 6 5 4 3 2 1 0 name clksl[1:0] type r r r r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:2 unused read = 000000b; write = don?t care 1:0 clksl[1:0] system clock source select bits. 00: sysclk derived from the internal oscilla tor and scaled per the ifcn bits in reg - ister oscicn. 01: sysclk derived from the external oscillator circuit. 10: sysclk derived from the clock multiplier. 11: reserved.
rev. 1.1 137 c8051f54x 17.2. programmable internal oscillator all c8051f54x devices include a prog rammable internal high-frequency os cillator that defaults as the sys- tem clock after a system rese t. the internal oscillator period can be adjusted via the oscicrs and osci- fin registers defined in sfr definition 17.3 and sf r definition 17.4. on c8051f54x devices, oscicrs and oscifin are factory calibrated to obtain a 24 mhz base frequency. note that the system clock may be derived from the programmed in ternal oscillator divided by 1, 2, 4, 8, 16, 32, 64, or 128, as defined by the ifcn bits in register oscicn. the divide value defaults to 128 following a reset. 17.2.1. internal os cillator suspend mode when software writes a logic 1 to suspend (oscicn.5) , the internal oscillator is suspended. if the sys- tem clock is derived from t he internal oscillator, the input clock to the peripheral or cip-51 will be stopped until one of the following events occur: ? port 0 match event. ? port 1 match event. ? port 2 match event. ? port 3 match event. ? comparator 0 enabled and output is logic 0. when one of the oscillator awakening events occur, the internal oscillato r, cip-51, and affe cted peripherals resume normal operation, regardless of whether the event also causes an interrupt. the cpu resumes execution at the instruction fo llowing the write to suspend. note: when entering suspend mode, firmware must set t he ztcen bit in ref0cn (sfr definition 7.1).
c8051f54x 138 rev. 1.1 sfr address = 0xa1; sfr page = 0x0f; sfr definition 17.2. oscicn: internal os cillator control bit 7 6 5 4 3 2 1 0 name ioscen[1:0] suspend ifrdy reserved ifcn[2:0] type r/w r/w r/w r r r/w reset 1 1 0 1 0 0 0 0 bit name function 7:6 ioscen[1:0] internal oscillator enable bits. 00: oscillator disabled. 01: reserved. 10: reserved. 11: oscillator enabled in normal mode and disabled in suspend mode. 5 suspend internal oscillator suspend enable bit. setting this bit to logic 1 places the in ternal oscillator in suspend mode. the inter - nal oscillator resumes operation when one of the suspend mode awakening events occurs. 4 ifrdy internal oscillator frequency ready flag. 0: internal oscillator is not running at progr ammed frequency. 1: internal oscillator is ru nning at programmed frequency. 3 reserved read = 0b; write = 0b. 2:0 ifcn[2:0] internal oscillator freque ncy divider control bits. 000: sysclk derived from internal oscillator divided by 128. 001: sysclk derived from internal oscillator divided by 64. 010: sysclk derived from internal oscillator divided by 32. 011: sysclk derived from inte rnal oscillator divided by 16. 100: sysclk derived from intern al oscillator divided by 8. 101: sysclk derived from intern al oscillator divided by 4. 110: sysclk derived from inte rnal oscillator divided by 2. 111: sysclk derived from inte rnal oscillator divided by 1.
rev. 1.1 139 c8051f54x sfr address = 0xa2; sfr page = 0x0f; sfr address = 0x9e; sfr page = 0x0f; sfr definition 17.3. oscicrs: internal osci llator coarse calibration bit 7 6 5 4 3 2 1 0 name oscicrs[6:0] type r r/w reset 0 varies varies varies varies varies varies varies bit name function 7 unused read = 0; write = don?t care 6:0 oscicrs[6:0] internal oscillator co arse calibration bits. these bits determine the internal oscilla tor period. when se t to 0000000b, the internal oscillato r operates at its slowest setting. when set to 11 11111b, the inter - nal oscillator operates at its fastest sett ing. the reset value is factory calibrated to generate an internal oscillator frequency of 24 mhz. sfr definition 17.4. oscifin: internal oscill ator fine calibration bit 7 6 5 4 3 2 1 0 oscifin[5:0] type r r r/w reset 0 0 varies varies varies varies varies varies bit name function 7:6 unused read = 00b; write = don?t care 5:0 oscifin[5:0] internal oscillator fi ne calibration bits. these bits are fine adjustment for the inte rnal oscillator period. the reset value is factory calibrated to generate an internal oscillator frequency of 24 mhz.
c8051f54x 140 rev. 1.1 17.3. clock multiplier the clock multiplier generates an out put clock which is 4 times the input clock frequency scaled by a pro- grammable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7. the clock multiplier?s input can be selected from the external o scillator, or the internal or external oscillators divided by 2. this produces three possible base outputs which can be scaled by a programmable factor: in ternal oscillator x 2, external oscillator x 2, or external oscillator x 4. see section 17.1 on page 135 for details on system clock selec- tion. the clock multiplier is configured vi a the clkmul register (sfr defi nition 17.5). the procedure for con- figuring and enabling the cloc k multiplier is as follows: 1. reset the multiplier by writ ing 0x00 to register clkmul. 2. select the multiplier input source via the mulsel bits. 3. select the multiplier output scaling factor via the muldiv bits 4. enable the multiplier with the mulen bit (clkmul | = 0x80). 5. delay for >5 s. 6. initialize the multip lier with the mulinit bit (clkmul | = 0xc0). 7. poll for mulrdy > 1. important note : when using an external oscillator as the input to the clock multiplier, the external source must be enabled and stable before th e multiplier is initialized. see ?17.4. external oscillator drive circuit? on page 142 for details on select ing an external oscillator source. the clock multiplier allows faster op eration of the cip-51 core and is intended to generate an output fre- quency between 25 and 50 mhz. the clock multiplier ca n also be used with slow input clocks. however, if the clock is below the minimum cl ock multiplier input frequency (fcm min ), the generated clock will consist of four fast pulses followed by a long delay until t he next input clock rising edge. the average frequency of the output is equal to 4x the input, but the instantan eous frequency may be faster. see figure 17.2 below for more information. figure 17.2. example clock multiplier output if f cm >= f cm min in f cm in f cm out if f cm < f cm min in f cm out f cm in
rev. 1.1 141 c8051f54x sfr address = 0x97; sfr page = 0x0f; sfr definition 17.5. clkmul: clock multiplier bit 7 6 5 4 3 2 1 0 name mulen mulinit mulrdy muldiv[2:0] mulsel[1:0] type r/w r/w r r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 mulen clock multiplier enable. 0: clock multiplier disabled. 1: clock mult iplier enabled. 6 mulinit clock multiplier initialize. this bit is 0 when the clock multiplier is enabled. once enabled, writing a 1 to this bit will initialize the clock multiplier. th e mulrdy bit reads 1 when the clock mul - tiplier is stabilized. 5 mulrdy clock multiplier ready. 0: clock multiplier is not ready. 1: clock multiplier is ready (pll is locked). 4:2 muldiv[2:0] clock multiplier output scaling factor. 000: clock multiplier output scaled by a factor of 1. 001: clock multiplier output scaled by a factor of 1. 010: clock multiplier output scaled by a factor of 1. 011: clock multiplier output scaled by a factor of 2/3*. 100: clock multiplier output scaled by a factor of 2/4 (1/2). 101: clock multiplier output scaled by a factor of 2/5*. 110: clock multiplier output sc aled by a factor of 2/6 (1/3). 111: clock multiplier output scaled by a factor of 2/7*. *note: the clock multiplier output duty cycle is not 50% for these settings. 1:0 mulsel[1:0] clock multiplier input select. these bits select the clock su pplied to the clock multiplier mulsel[1:0] selected input clock clock multiplier output for muldiv[2:0] = 000b 00 internal oscillator internal oscillator x 2 01 external oscillator external oscillator x 2 10 internal oscillator internal oscillator x 4 11 external oscillator external oscillator x 4 notes: the maximum system clock is 50 mhz, and so the clock multiplier output should be scaled accordingly. ? if internal oscillator x 2 or external oscillator x 2 is select ed using the mulsel bits, muldiv[2:0] is ignored.
c8051f54x 142 rev. 1.1 17.4. external osci llator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. for a cr ystal or ceramic resonator configuration, the crys- tal/resonator must be wired across the xtal1 and xt al2 pins as shown in opti on 1 of figure 17.1. a 10 m ?? resistor also must be wired across the xtal2 an d xtal1 pins for the crystal/resonator configura- tion. in rc, capacitor, or cmos cl ock configuration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 17.1. the type of external oscillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see sfr definition 17.6). important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal/r esonator mode, port pins p0.2 and p0.3 are used as xtal1 and xtal2 respectively. when the ex ternal oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is used as xtal2. the port i/o crossbar should be configured to skip the port pins used by the oscillator circuit; see sectio n ?18.3. priority crossbar decoder? on page 150 for crossbar co nfiguration. additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as analog inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?18.4. port i/o initialization? on page 152 for de tails on port inpu t mode selection.
rev. 1.1 143 c8051f54x sfr address = 0x9f; sfr page = 0x0f; sfr definition 17.6. oscxcn: external oscillator control bit 7 6 5 4 3 2 1 0 name xtlvld xoscmd[2:0] xfcn[2:0] type r r/w r r/w reset 0 0 0 0 0 0 0 0 bit name function 7 xtlvld crystal oscillator valid flag. (read only when xoscmd = 11x.) 0: crystal oscillator is u nused or not yet stable. 1: crystal oscillator is running and stable. 6:4 xoscmd[2:0] external oscillat or mode select. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. 3 unused read = 0b; write =0b 2:0 xfcn[2:0] external oscillator frequency control bits. set according to the desired frequency for crystal or rc mode. set according to the desired k factor for c mode. xfcn crystal mode rc mode c mode 000 f ? 32 khz f ?? 25 khz k factor = 0.87 001 32 khz ?? f ?? 84 khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 84 khz ? f ?? 225 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 225 khz ? f ?? 590 khz 100 khz ?? f ?? 200 khz k factor = 22 100 590 khz ? f ?? 1.5 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.5 mhz ? f ?? 4 mhz 400 khz ?? f ?? 800 khz k factor = 180 110 4 mhz ? f ?? 10 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 10 mhz ? f ?? 30 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590
c8051f54x 144 rev. 1.1 17.4.1. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 17.1 , option 1. the external oscillato r frequency contro l value (xfcn) should be chosen from the crystal column of the ta ble in sfr definition 17.6 (oscxcn register). for example, an 11.0592 mhz crystal requires an xfcn setting of 111b and a 32.768 khz watch crystal requires an xfcn setting of 001b. after an external 32.768 khz oscillator is st abilized, the xfcn setting can be switched to 000 to save power. it is recommended to enable the missing clock detector before switching the system clock to any external oscillator source. when the crystal oscillator is first e nabled, the oscillator amplitude detecti on circuit requires a settling time to achieve proper bias. introduc ing a delay of 1 ms between enab ling the oscillator and checking the xtlvld bit will prevent a premature switch to the extern al oscillator as the system clock. switching to the external oscillator before the crysta l oscillator has stabilized can result in unpredictable behavior. the rec- ommended procedure is: 1. force xtal1 and xtal2 to a high state. this involv es enabling the crossbar and writing 1 to the port pins associated with xtal1 and xtal2. 2. configure xtal1 and xtal2 as analog inputs using. 3. enable the external oscillator. 4. wait at least 1 ms. 5. poll for xtlvld => 1. 6. enable the missing clock detector. 7. switch the system clock to the external oscillator. important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces which could introduce noise or interference. the capacitors shown in the external crystal configur ation provide the load capacitance required by the crystal for correct oscillation. these capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the xtal1 and xtal2 pins. note: the desired load capacitance depends upon the crystal an d the manufacturer. refer to the crystal data sheet when completing these calculations. for example, a tuning-fork crystal of 32.768 khz wi th a recommended load capacitance of 12.5 pf should use the configuration shown in figure 17.1, option 1. the total value of the capacitors and the stray capac- itance of the xtal pins should equal 25 pf. with a stra y capacitance of 3 pf per pin, the 22 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 17.3.
rev. 1.1 145 c8051f54x figure 17.3. external 32.768 khz quartz crystal oscillator connection diagram 17.4.2. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 17.1, option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter- mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscilla tion, according to equation , where f = the frequency of oscillation in mh z, c = the capacitor value in pf, an d r = the pull-up resistor value in k ? . equation 17.1. rc mode oscillator frequency for example: if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23(10 3 )/rc = 1.23(10 3 )/[246 x 50] = 0.1 mhz = 100 khz referring to the table in sfr definition 17.6, the required xfcn setting is 010b. 17.4.3. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 17.1, option 3. the capacitor should be no gr eater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasiti c capacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci- tor to be used and find the frequency of oscillation according to equation 17.2, where f = the frequency of oscillation in mhz, c = the capacitor value in pf, and v dd = the mcu power supply in volts. xtal1 xtal2 10m ? 22pf* 22pf* 32.768 khz * capacitor values depend on crystal specifications f1.2310 3 ? rc ? ?? ? =
c8051f54x 146 rev. 1.1 equation 17.2. c mode oscillator frequency for example: assume v dd = 2.1 v and f = 75 khz: f = kf / (c x vdd) ? 0.075 mhz = kf / (c x 2.1) since the frequency of roughly 75 khz is desired, select the k factor from the table in sfr definition 17.6 (oscxcn) as kf = 7.7: 0.075 mhz = 7.7 / (c x 2.1) ? c x 2.1 = 7.7 / 0.075 mhz ? c = 102.6 / 2.0 pf = 51.3 pf therefore, the xfcn value to use in this example is 010b. fkf ?? rv dd ? ?? ? =
rev. 1.1 147 c8051f54x 18. port input/output digital and analog resources are available through 25 (c8051f540/1/4/5) or 18 (c8051f542/3/6/7) i/o pins. port pins p0.0-p3.0 on the c8051f540/1/4/5 an d port pins p0.0-p2.1 on the c8051f542/3/6/7 can be defined as general-purpose i/o (gpio), assigned to o ne of the internal digital resources, or assigned to an analog function as shown in figure 18.3. port pi n p3.0 on the c8051f540/1/4/5 can be used as gpio and is shared with the c2 interface data signal (c2d). similarly, port pin p2.1 is shared with c2d on the c8051f542/3/6/7. the designer has complete control ov er which functions are a ssigned, limited only by the number of physical i/o pins. this resource assignment flexibility is achieved through the use of a prior- ity crossbar decoder. the state of a port i/o pin c an always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital reso urces to the i/o pins based on the priority decoder (figure 18.3 and figure 18.4). the registers xbr0, xbr1, xbr2 are defined in sfr definition 18.1 and sfr definition 18.2 and are used to select internal digital functions. the port i/o cells are configured as either push-pu ll or open-drain in the port output mode registers (pnmdout, where n = 0,1). complete electrical specifications for port i/o are given in table 6.3 on page 51. figure 18.1. port i/o functional block diagram external pins digital crossbar priority decoder spi0 uart0 cp0 t0, t1, /int0, /int1 p1.0 p1.7 p2.0 p2.7 p0.0 p0.7 highest priority lowest priority 8 8 cp1 (internal digital signals) smbus0 p3.0 8 8 pnmdout, pndmin registers xbr0, xbr1, xbr2, pnskip p1 i/o cells p3 i/o cell p0 i/o cells p2 i/o cells pca0 7 lin0 2 pnmask pnmatch registers /sysclk 4 lowest priority highest priority port latches p0 p1 p2 p3 25 (px.0-px.7) 2 2 2 4 2
c8051f54x 148 rev. 1.1 18.1. port i/o m odes of operation port pins p0.0?p3.0 use the port i/o cell shown in fi gure 18.2. each port i/o cell can be configured by software for analog i/o or digital i/o using the pnmdin registers. on rese t, all port i/o ce lls default to a high impedance state with weak pull-ups enabled unt il the crossbar is enabled (xbare = 1). 18.1.1. port pins conf igured for analog i/o any pins to be used as comparator or adc inputs, ex ternal oscillator inputs, or vref should be config- ured for analog i/o (pnmdin.n = 0). when a pin is configured for analog i/o, its weak pullup, digital driver, and digital receiver are disabled. port pins configur ed for analog i/o will always read back a value of 0. configuring pins as analog i/o saves power and isolates the port pin from digital interference. port pins configured as digital inputs may still be used by analog peripherals; howe ver, this practice is not recom- mended and may result in measurement errors. 18.1.2. port pins configured for digital i/o any pins to be used by digital peripherals (uart, sp i, smbus, etc.), external digital event capture func- tions, or as gpio should be configured as digital i/o (pnmdin.n = 1). for digital i/o pins, one of two output modes (push-pull or open-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = 1) drive the port pad to the vio or gnd supply rails based on the output logic value of the port pin. open-drain outputs have the high side driver disabled; therefore, they only drive the port pad to gnd when the output logic value is 0 and become high impedance inputs (both high low drivers turned off) when the output logic value is 1. when a digital i/o cell is placed in the high impedance st ate, a weak pull-up transistor pulls the port pad to the vio supply voltage to ensure the digital input is at a defined logic state. weak pull-ups are disabled when the i/o cell is driven to gnd to minimize power consumption and may be globally disabled by setting weakpud to 1. the user should ensure that digital i/o ar e always internally or ex ternally pulled or driven to a valid logic state to minimize power consumption. port pins configured for digital i/o always read back the logic state of the port pad, regardless of the output logic value of the port pin. figure 18.2. port i/o cell block diagram gnd vio vio (weak) port pad to/from analog peripheral pxmdin.x (1 for digital) (0 for analog) px.x ? output logic value (port latch or crossbar) xbare (crossbar enable) px.x ? input logic value (reads 0 when pin is configured as an analog i/o) pxmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable)
rev. 1.1 149 c8051f54x 18.1.3. interfacing port i/o in a multi-voltage system all port i/o are capable of interfacing to digital logic operating at a supply voltage higher than v dd and less than 5.25 v. connect the v io pin to the voltage source of the interface logic. 18.2. assigning port i/o pins to analog and digital functions port i/o pins p0.0?p3.0 can be assigned to various a nalog, digital, and external interrupt functions. the port pins assigned to analog functions should be config ured for analog i/o, and port pins assigned to digi- tal or external interrupt functions should be configured for digital i/o. 18.2.1. assigning port i/o pins to analog functions ta b l e 18.1 shows all available analog function s that require port i/o assignments. port pins selected for these analog functions should have their corresponding bit in pnskip set to 1. this reserves the pin for use by the analog function and does not allow it to be claimed by the crossbar. ta b l e 18.1 shows the potential mapping of port i/o to each analog function. 18.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assigned to digital functi ons or used as gpio. most digital functions rely on the crossbar for pin assi gnment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. port pins used by these digital func- tions and any port pins selected for use as gpio should have their corresponding bit in pnskip set to 1. table 18.2 shows all available digital functions and the potential mapping of port i/o to each digital function. table 18.1. port i/o assignment for analog functions analog function potentially assignable port pins sfr(s) used for assignment adc input p0.0?p3.0* adc0mx, pnskip comparator0 or compartor1 input p0.0?p2.7* cpt0mx, cpt1mx, pnskip voltage reference (vref0) p0.0 ref0cn, pnskip external oscillator in crystal mode (xtal1) p0.2 oscxcn, pnskip external oscillator in rc, c, or crystal mode (xtal2) p0.3 oscxcn, pnskip *note: p2.2-p2.7, p3.0 are only available on the 32-pin packages table 18.2. port i/o assignment for digital functions digital function potentially assignable port pins sfr(s) used for assignment uart0, spi0, smbus, lin0, cp0, cp0a, cp1, cp1a, sysclk, pca0 (cex0-5 and eci), t0 or t1. any port pin available for assignment by the crossbar. this includes p0.0?p3.0* pins which have their pnskip bit set to 0. note: the crossbar will always assign uart0 pins to p0.4 and p0.5. xbr0, xbr1, xbr2 *note: p2.2-p2.7, p3.0 are only available on the 32-pin packages.
c8051f54x 150 rev. 1.1 18.2.3. assigning port i/o pins to external digital event capture functions external digital event captur e functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital i/o pin. the digital event capture functions do not require dedicated pins and will function on both gpio pins (pnskip = 1) and pi ns in use by the crossbar (pnskip = 0). external digital event capt ure functions cannot be used on pins configured for analog i/o. ta b l e 18.3 shows all available external digital event capture functions. 18.3. priority crossbar decoder the priority crossbar decoder (figure 18.3) assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the leas t-significant unassigned port pin is assigned to that resource excluding uart0, which is always assigned to pins p0.4 and p0. if a port pin is assigned, the crossbar skips that pin when assign ing the next selected reso urce. additionally, the cr ossbar will skip port pins whose associated bits in the pnskip registers are set. the pnskip registers allow software to skip port pins that are to be used for analog input, dedicated functions, or gpio. because of the nature of priority crossbar decoder, not all peripherals can be located on all port pins. figure 18.3 maps peripherals to the potential port pins on which the peripheral i/o can appear. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. th is applies to p0.0 if vref is used, p0.1 if the adc is configured to use the external conversion start signal (cnvstr), p0.3 and/or p0.2 if the external oscillator circuit is enabled, and any selected adc or comparator inputs. the crossbar skips selected pins as if they were already assigned, a nd moves to the next unassigned pin. any pin used for gpio p0.0?p3.0* p0skip, p1skip, p2skip, p3skip table 18.3. port i/o assignment for external digital event capture functions digital function potentially assignable port pins sfr(s) used for assignment external interrupt 0 p1.0?p1.7 it01cf external interrupt 1 p1.0?p1.7 it01cf port match p0.0?p3.0* p0mask, p0mat p1mask, p1mat p2mask, p2mat p3mask, p3mat *note: p2.2-p2.7, p3.0 are only available on the 32-pin packages. table 18.2. port i/o assignment for digital functions digital function potentially assignable port pins sfr(s) used for assignment *note: p2.2-p2.7, p3.0 are only available on the 32-pin packages.
rev. 1.1 151 c8051f54x figure 18.3. peripheral availability on port i/o pins registers xbr0, xbr1, and xbr2 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the cr ossbar assigns both pins associated with the smbus (sda and scl); and similarly when the uart or lin ar e selected, the crossbar assigns both pins associ- ated with the peripheral (tx and rx). uart0 pin assignments are fixed for bootloading purposes: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standard port i/os appear contig- uously after the prioritized functions have been assigned. important note: the spi can be operated in either 3-wire or 4-wire modes, pending the state of the nssmd1?nssmd0 bits in register spi0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. as an example configuration, if spi0 in 4-wire mode , and pca0 modules 0, 1, and 2 are enabled on the crossbar with p0.1, p0.2, and p0.5 skipped, the registers should be set as follows: xbr0 = 0x04 (spi0 enabled), xbr1 = 0x0c (pca0 modules 0, 1, and 2 enabled), xbr2 = 0x40 (crossbar enabled), and p0skip = 0x26 (p0.1, p0.2, and p0.5 skipped). th e resulting crossbar wo uld look as shown in figure 18.4. port p3 special function signals vref cnvstr xtal1 xtal2 ale /rd /wr pin i/o 0123456701234567012345670 uart_tx uart_rx sck miso mosi nss sda scl cp0 cp0a cp1 cp1a sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 lin_tx lin_rx p0 p1 p2 p2.2-p2.7, p3.0 only available on the 32-pin packages
c8051f54x 152 rev. 1.1 figure 18.4. crossbar priority decoder in example configuration 18.4. port i/o initialization port i/o initialization cons ists of the following steps: 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). 2. select the output mode (open-drain or push-pull) fo r all port pins, using the port output mode register (pnmdout). 3. select any pins to be skipped by the i/o cr ossbar using the port skip registers (pnskip). 4. assign port pins to desired peripherals. 5. enable the cro ssbar (xbare = 1). all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this process save s power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. additionally, all analog input pins should be configur ed to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a 1 indicates a digital input, and a 0 indicates an analog input. all pins default to digital inputs on reset. see sfr definition 18.13 for the pnmdin register details. port p3 special function signals vref cnvstr xtal1 xtal2 ale /rd /wr pin i/o 012345670123456701234567 0 uart_tx uart_rx sck miso mosi nss *nss is only pinned out in 4-wire spi mode sda scl cp0 cp0a cp1 cp1a sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 lin_tx lin_rx 011001000000000000000000 0 p3skip[0] p2 p2skip[0:7] p2.2-p2.7, p3.0 only available on the 32-pin packages p0 p1 p0skip[0:7] p1skip[0:7]
rev. 1.1 153 c8051f54x the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bit in xbr2 is 0, a weak pullup is enabled for all po rt i/o config- ured as open-drain. weakpu d does not affect the pu sh-pull port i/o. furthe rmore, the weak pullup is turned off on an output that is driving a 0 to avoid unnecessary power dissipation. registers xbr0, xbr1, and xbr2 must be loaded with t he appropriate values to select the digital i/o functions required by the design. setting the xbare bit in xbr2 to 1 enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, on e can determine the i/o pin-out using the priority decode table; as an alternative, th e configuration wizard utility of the silicon labs ide software will deter- mine the port i/o pin-assignments based on the xbrn register settings. the crossbar must be enabled to us e port pins as standard port i/o in output mode. port output drivers are disabled while the crossbar is disabled.
c8051f54x 154 rev. 1.1 sfr address = 0xe1; sfr page = 0x0f sfr definition 18.1. xbr0: port i/o crossbar register 0 bit 7 6 5 4 3 2 1 0 name cp1ae cp1e cp0ae cp0e smb0e spi0e reserved urt0e type r/w r/w r/w r/w r/w r/w r r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cp1ae comparator1 asynchronous output enable. 0: asynchronous cp1 unavailable at port pin. 1: asynchronous cp1 routed to port pin. 6 cp1e comparator1 output enable. 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. 5 cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. 4 cp0e comparator0 output enable. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. 3 smb0e smbus i/o enable. 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. 2 spi0e spi i/o enable. 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that the spi can be assigned either 3 or 4 gpio pins. 1 reserved always write to 0. 0 urt0e uart i/o output enable. 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5.
rev. 1.1 155 c8051f54x sfr address = 0xe2; sfr page = 0x0f sfr definition 18.2. xbr1: port i/o crossbar register 1 bit 7 6 5 4 3 2 1 0 name t1e t0e ecie pca0me[2:0] syscke reserved type r/w r/w r/w r/w r/w r r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 t1e t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. 6 t0e t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. 5 ecie pca0 external counter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. 4:2 pca0me[2:0] pca module i/o enable bits. 000: all pca i/o unavailable at port pins. 001: cex0 routed to port pin. 010: cex0, cex1 routed to port pins. 011: cex0, cex1, cex2 routed to port pins. 100: cex0, cex1, cex2, cex3 routed to port pins. 101: cex0, cex1, cex2, cex3, cex4 routed to port pins. 110: cex0, cex1, cex2, cex3, cex4, cex5 routed to port pins. 111: reserved 1 syscke sysclk output enable. 0: sysclk unavailable at port pin. 1: sysclk output routed to port pin. 0 reserved always write to 0.
c8051f54x 156 rev. 1.1 sfr address = 0xc7; sfr page = 0x0f sfr definition 18.3. xbr2: port i/o crossbar register 1 bit 7 6 5 4 3 2 1 0 name weakpud xbare reserved lin0e type r/w r/w r/w r/w r/w r r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured for analog mode). 1: weak pullups disabled. 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5:1 reserved always write to 00000b. 0 lin0e lin i/o output enable. 0: lin i/o unavailable at port pin. 1: lin_tx, lin_rx routed to port pins.
rev. 1.1 157 c8051f54x 18.5. port match port match functionality allows system events to be tr iggered by a logic value change on p0, p1, p2 or p3. a software controlled value stored in the pnmatch registers specifies the expected or normal logic values of p0, p1, p2, and p3. a port mismatch event occurs if the logic levels of the port?s input pins no longer match the software controlled value. this allows software to be notified if a certain change or pattern occurs on p0, p1, p2, or p3 input pins regardless of the xbrn settings. the pnmask registers can be used to individually select which of th e port pins should be compared against the pnmatch registers. a port mismatch event is generated if (pn & pnmask) does not equal (pnmatch & pnmask), where n is 0, 1, 2 or 3 a port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as idle or suspend. see the interrupts and power options chapte rs for more details on interrupt and wake-up sources. sfr address = 0xf2; sfr page = 0x00 sfr address = 0xf1; sfr page = 0x00 sfr definition 18.4. p0mask: port 0 mask register bit 7 6 5 4 3 2 1 0 name p0mask[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 p0mask[7:0] port 0 mask value. selects p0 pins to be compared to the corresponding bits in p0mat. 0: p0.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p0.n pin logic value is compared to p0mat.n. sfr definition 18.5. p0mat: port 0 match register bit 7 6 5 4 3 2 1 0 name p0mat[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 p0mat[7:0] port 0 match value. match comparison value used on port 0 for bits in p0mat which are set to 1. 0: p0.n pin logic value is compared with logic low. 1: p0.n pin logic value is compared with logic high.
c8051f54x 158 rev. 1.1 sfr address = 0xf4; sfr page = 0x00 sfr address = 0xf3; sfr page = 0x00 sfr definition 18.6. p1mask: port 1 mask register bit 7 6 5 4 3 2 1 0 name p1mask[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 p1mask[7:0] port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p1.n pin logic value is compared to p1mat.n. sfr definition 18.7. p1mat: port 1 match register bit 7 6 5 4 3 2 1 0 name p1mat[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 p1mat[7:0] port 1 match value. match comparison value used on port 1 for bits in p1mat which are set to 1. 0: p1.n pin logic value is compared with logic low. 1: p1.n pin logic value is compared with logic high.
rev. 1.1 159 c8051f54x sfr address = 0xb2; sfr page = 0x00 sfr address = 0xb1; sfr page = 0x00 sfr definition 18.8. p2mask: port 2 mask register bit 7 6 5 4 3 2 1 0 name p2mask[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 p2mask[7:0] port 2 mask value. selects p2 pins to be compared to the corresponding bits in p2mat. 0: p2.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p2.n pin logic value is compared to p2mat.n. note: ports 2.2-p2.7 only available on 32-pin packages. sfr definition 18.9. p2mat: port 2 match register bit 7 6 5 4 3 2 1 0 name p2mat[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 p2mat[7:0] port 2 match value. match comparison value used on port 2 for bits in p2mat which are set to 1. 0: p2.n pin logic value is compared with logic low. 1: p2.n pin logic value is compared with logic high. note: ports 2.2-p2.7 only available on 32-pin packages.
c8051f54x 160 rev. 1.1 sfr address = 0xaf; sfr page = 0x00 sfr address = 0xae ; sfr page = 0x00 sfr definition 18.10. p3mask: port 3 mask register bit 7 6 5 4 3 2 1 0 name 0 0 0 0 0 0 0 p3mask[0] type r r r r r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:1 unused read = 0000000b; write = don?t care. 0 p3mask[7:0] port 3 mask value. selects p3.n pins to be compared to the corresponding bits in p3mat. 0: p3.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p3.n pin logic value is compared to p3mat.n. note: p3.0 is only available on the 32-pin packages. sfr definition 18.11. p3mat: port 3 match register bit 7 6 5 4 3 2 1 0 name 0 0 0 0 0 0 0 p3mat[0] type r r r r r r r r/w reset 1 1 1 1 1 1 1 1 bit name function 7:1 unused read = 0000000b; write = don?t care. 0 p3mat[0] port 3 match value. match comparison value used on port 3 for bits in p3mat which are set to 1. 0: p3.n pin logic value is compared with logic low. 1: p3.n pin logic value is compared with logic high. note: p3.0 is only available on the 32-pin packages.
rev. 1.1 161 c8051f54x 18.6. special function re gisters for accessing an d configuring port i/o all port i/o are accessed through corresponding specia l function registers (sfrs) that are both byte addressable and bit addressable. when writing to a port, the value writt en to the sfr is latched to main- tain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pi n is assigned to another signal by the crossbar, the port register can always read its corresponding port i/ o pin). the exception to this is the execution of the read-modify-write instructio ns that target a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the fo llowing: anl, orl, xrl, jb c, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an indi vidual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. ports 0?3 have a corresponding pnskip register which allows its individual port pins to be assigned to dig- ital functions or skipped by the crossbar. all port pins used for analog functions, gpio, or dedicated digital functions such as the emif shou ld have their pnskip bit set to 1. the port input mode of the i/o pins is defined usi ng the port input mode registers (pnmdin). each port cell can be configured for analog or digital i/o. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. sfr address = 0x80; sfr page = all pages; bit-addressable sfr definition 18.12. p0: port 0 bit 7 6 5 4 3 2 1 0 name p0[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name description write read 7:0 p0[7:0] port 0 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p0.n port pin is logic low. 1: p0.n port pin is logic high.
c8051f54x 162 rev. 1.1 sfr address = 0xf1; sfr page = 0x0f sfr address = 0xa4; sfr page = 0x0f sfr definition 18.13. p0mdin: port 0 input mode bit 7 6 5 4 3 2 1 0 name p0mdin[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 p0mdin[7:0] analog configuration bits for p0.7?p0.0 (respectively). port pins configured for analog mode have their weak pull-up and digital receiver disabled. for analog mode, the pin also needs to be configured for open-drain mode in the p0mdout register. 0: corresponding p0.n pin is configured for analog mode. 1: corresponding p0.n pin is not configured for analog mode. sfr definition 18.14. p0mdout: port 0 output mode bit 7 6 5 4 3 2 1 0 name p0mdout[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 p0mdout[7:0] output configuration bits for p0.7?p0.0 (respectively). these bits are ignored if the correspondi ng bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull.
rev. 1.1 163 c8051f54x sfr address = 0xd4; sfr page = 0x0f sfr address = 0x90; sfr page = all pages; bit-addressable sfr definition 18.15. p0skip: port 0 skip bit 7 6 5 4 3 2 1 0 name p0skip[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 p0skip[7:0] port 0 crossbar skip enable bits. these bits select port 0 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. sfr definition 18.16. p1: port 1 bit 7 6 5 4 3 2 1 0 name p1[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name description write read 7:0 p1[7:0] port 1 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p1.n port pin is logic low. 1: p1.n port pin is logic high.
c8051f54x 164 rev. 1.1 sfr address = 0xf2; sfr page = 0x0f sfr address = 0xa5; sfr page = 0x0f sfr definition 18.17. p1mdin: port 1 input mode bit 7 6 5 4 3 2 1 0 name p1mdin[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 p1mdin[7:0] analog configuration bits for p1.7?p1.0 (respectively). port pins configured for analog mode have their weak pull-up and digital receiver disabled. for analog mode, the pin also needs to be configured for open-drain mode in the p1mdout register. 0: corresponding p1.n pin is configured for analog mode. 1: corresponding p1.n pin is not configured for analog mode. sfr definition 18.18. p1mdout: port 1 output mode bit 7 6 5 4 3 2 1 0 name p1mdout[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 p1mdout[7:0] output configuration bits for p1.7?p1.0 (respectively). these bits are ignored if the correspondi ng bit in register p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull.
rev. 1.1 165 c8051f54x sfr address = 0xd5; sfr page = 0x0f sfr address = 0xa0; sfr page = all pages; bi t-addressable sfr definition 18.19. p1skip: port 1 skip bit 7 6 5 4 3 2 1 0 name p1skip[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 p1skip[7:0] port 1 crossbar skip enable bits. these bits select port 1 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. sfr definition 18.20. p2: port 2 bit 7 6 5 4 3 2 1 0 name p2[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name description write read 7:0 p2[7:0] port 2data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p2.n port pin is logic low. 1: p2.n port pin is logic high. note: p2.2-p2.7 are only available on the 32-pin packages.
c8051f54x 166 rev. 1.1 sfr address = 0xf3; sfr page = 0x0f sfr address = 0xa6; sfr page = 0x0f sfr definition 18.21. p2mdin: port 2 input mode bit 7 6 5 4 3 2 1 0 name p2mdin[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 p2mdin[7:0] analog configuration bits for p2.7?p2.0 (respectively). port pins configured for analog mode have their weak pull-up and digital receiver disabled. for analog mode, the pin also needs to be configured for open-drain mode in the p2mdout register. 0: corresponding p2.n pin is configured for analog mode. 1: corresponding p2.n pin is not configured for analog mode. note: p2.2-p2.7 are only available on the 32-pin packages. sfr definition 18.22. p2mdout: port 2 output mode bit 7 6 5 4 3 2 1 0 name p2mdout[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 p2mdout[7:0] output configuration bits for p2.7?p2.0 (respectively). these bits are ignored if the correspondi ng bit in register p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. note: p2.2-p2.7 are only available on the 32-pin packages.
rev. 1.1 167 c8051f54x sfr address = 0xd6; sfr page = 0x0f sfr address = 0xb0; sfr page = all pages; bi t-addressable sfr definition 18.23. p2skip: port 2 skip bit 7 6 5 4 3 2 1 0 name p2skip[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 p2skip[7:0] port 2 crossbar skip enable bits. these bits select port 2 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar. note: p2.2-p2.7 are only available on the 32-pin packages. sfr definition 18.24. p3: port 3 bit 7 6 5 4 3 2 1 0 name p3 type r r r r r r r r/w reset 1 1 1 1 1 1 1 1 bit name description write read 7:1 unused read = 0000000b; write = don?t care. 0 p3[0] port 3 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p3.n port pin is logic low. 1: p3.n port pin is logic high. note: port p3.0 is only available on the 32-pin packages.
c8051f54x 168 rev. 1.1 sfr address = 0xf4; sfr page = 0x0f sfr address = 0xae; sfr page = 0x0f sfr definition 18.25. p3mdin: port 3 input mode bit 7 6 5 4 3 2 1 0 name p3mdin[0] type r r r r r r r r/w reset 1 1 1 1 1 1 1 1 bit name function 7:1 unused read = 0000000b; write = don?t care. 0 p3mdin[0] analog configuration bits for p3.0. port pins configured for analog mode have their weak pull-up and digital receiver disabled. for analog mode, the pin also needs to be configured for open-drain mode in the p3mdout register. 0: corresponding p3.n pin is configured for analog mode. 1: corresponding p3.n pin is not configured for analog mode. note: port p3.0 is only available on the 32-pin packages. sfr definition 18.26. p3mdout: port 3 output mode bit 7 6 5 4 3 2 1 0 name p3mdout[0] type r r r r r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:1 unused read = 0000000b; write = don?t care. 7:0 p3mdout[7:0] output configuration bits for p3.0. these bits are ignored if the correspondi ng bit in register p3mdin is logic 0. 0: corresponding p3.n output is open-drain. 1: corresponding p3.n output is push-pull. note: port p3.0 is only available on the 32-pin packages.
rev. 1.1 169 c8051f54x sfr address = 0xd7; sfr page = 0x0f sfr definition 18.27. p3skip: port 3skip bit 7 6 5 4 3 2 1 0 name p3skip[0] type r r r r r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:1 unused read = 0000000b; write = don?t care. 0 p3skip[0] port 3 crossbar skip enable bits. these bits select port 3 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p3.n pin is not skipped by the crossbar. 1: corresponding p3.n pin is skipped by the crossbar. note: port p3.0 is only available on the 32-pin packages.
c8051f54x 170 rev. 1.1 19. local interconnect network (lin) important note: this chapter assumes an understanding of the local interconnect network (lin) proto- col. for more information about the lin protocol, including specifications, please refer to the lin consor- tium (http://www.lin-subbus.org). lin is an asynchronous, serial co mmunications interface us ed primarily in automotive networks. the sili- con laboratories lin controller is compliant to the 2. 1 specification, implements a complete hardware lin interface and includes the following features: ? selectable master and slave modes. ? automatic baud rate option in slave mode. ? the internal oscillator is accurate to within 0.5% of 24 mhz across th e entire temperat ure range and for vdd voltages greater than or equal to the minimum output of the on-chip voltage regulator, so an external oscillator is not necessary for mast er mode operation for most systems. note: the minimum system clock (sysclk) requir ed when using the li n controller is 8 mhz. figure 19.1. lin block diagram the lin controller has four main components: ? lin access registers?provide the interface between the mcu core and the lin controller. ? lin data registers?where transmitted and received message data bytes are stored. ? lin control registers?control the fu nctionality of the lin interface. ? control state machine and bit streaming logic?cont ains the hardware that serializes messages and controls the bus timing of the controller. c8051f540/2/4/6 indirectly addressed registers lin0adr lin0dat lin0cf lin data registers control state machine 8051 mcu core tx rx lin controller lin control registers
rev. 1.1 171 c8051f54x 19.1. software interfa ce with the lin controller the selection of the mode (master or slave) and the automatic baud rate feature are done though the lin0 control mode (lin0cf) register. the other lin regist ers are accessed indirectly through the two sfrs lin0 address (lin0adr) and lin0 data (lin0dat). th e lin0adr register selects which lin register is targeted by reads/writes of the lin0dat register. the fu ll list of indirectly-accessible lin registers is given in table 19.4 on page 179. 19.2. lin interface setup and operation the hardware based lin controller a llows for the implementation of both master and slave nodes with minimal firmware overhead and complete control of t he interface status while allowing for interrupt and polled mode operation. the first step to use the controller is to de fine the basic characte ristics of the node: mode?master or slave baud rate?either defined manually or using the autobaud feature (slave mode only) checksum type?select between classic or enhanced checksum, both of which are implemented in hard- ware. 19.2.1. mode definition following the lin specificatio n, the controller implements in hardware both the slave and master operating modes. the mode is configured using the mode bit (lin0cf.6). 19.2.2. baud rate options: manual or autobaud the lin controller can be selected to have its baud rate calculated manually or automatically. a master node must always have its baud rate set manually, but slave nodes can choose between a manual or auto- matic setup. the configur ation is selected using the abaud bit (lin0cf.5). both the manual and automatic baud rate configurati ons require additional setup. the following sections explain the different options available and their relati on with the baud rate, along with the steps necessary to achieve the required baud rate. 19.2.3. baud rate calculations: manual mode the baud rate used by the lin cont roller is a function of the system clock (sysclk) and the lin timing registers according to the following equation: the prescaler, divider and multiplier factors are pa rt of the lin0div and lin0mul registers and can assume values in the following range: important : the minimum system clock (sysclk) to operate the lin controller is 8 mhz. table 19.1. baud rate calculation variable ranges factor range prescaler 0?3 multiplier 0?31 divider 200?511 baud_rate sysclk 2 prescaler 1 + ?? divider multiplier 1 + ?? ? ? -------------------------------------------------------------------------------------------------------------------- - =
c8051f54x 172 rev. 1.1 use the following equations to calculate the values for the variables for the baud-rate equation: in all of these equations, the results must be rounded down to the nearest integer. the following example shows the steps for calculating th e baud rate values for a master node running at 24 mhz and communicating at 19200 bits/sec. first, calculate the multiplier: next, calculate the prescaler: finally, calculate the divider: these values lead to the following baud rate: the following code programs the interface in master mode, using the enhanced checksum and enables the interface to operate at 19230 bits /sec using a 24 mhz system clock. lin0cf = 0x80; // activate the interface lin0cf |= 0x40; // set the node as a master lin0adr = 0x0d; // point to the lin0mul register // initialize the register (prescaler, multiplier and bit 8 of divider) lin0dat = ( 0x01 << 6 ) + ( 0x00 << 1 ) + ( ( 0x138 & 0x0100 ) >> 8 ); lin0adr = 0x0c; // point to the lin0div register lin0dat = (unsigned char)_0x138; // initialize lin0div lin0adr = 0x0b; // point to the lin0size register lin0dat |= 0x80; // initialize the checksum as enhanced lin0adr = 0x08; // point to lin0ctrl register lin0dat = 0x0c; // reset any error and the interrupt table 19.2 includes the configuration values requ ired for the typical system clocks and baud rates: multiplier 20000 baud_rate ----------------------------- 1 ? = prescaler ln sysclk multiplier 1 + ?? baud_rate 200 ? ? ------------------------------------------------------------------------------------------------ 1 ln2 -------- 1 ? ? = divider sysclk 2 prescaler 1 + ?? multiplier 1 + ?? ? baud_rate ? ?? ------------------------------------------------------------------------------------------------------------------------------- ------ - = multiplier 20000 19200 ---------------- 1 0 . 0 4 1 7 0 ? = ? = prescaler ln 24000000 01 + ?? 19200 200 ? ? ----------------------------------------------------------- 1 ln2 -------- 1 ? ? 1.644 =1 ? = divider 24000000 2 11 + ?? 01 + ?? ? 19200 ? ---------------------------------------------------------------------- - 312.5 312 ? == baud_rate 24000000 2 11 + ?? 01 + ?? ? 312 ? ---------------------------------------------------------------- 19230.77 ? =
rev. 1.1 173 c8051f54x 19.2.4. baud rate calculations?automatic mode if the lin controller is configured for slave mode, on ly the prescaler and divider need to be calculated: the following example calculates the values of these variables for a 24 mhz system clock: table 19.3 presents some typical values of syst em clock and baud rate along with their factors. table 19.2. manual baud rate parameters examples baud (bits/sec) 20 k 19.2 k 9.6 k 4.8 k 1 k sysclk (mhz) mult. pres. div. mult. pres. div. mult. pres. div. mult. pres. div. mult. pres. div. 25 0 1 312 0 1 325 1 1 325 3 1 325 19 1 312 24.5 0 1 306 0 1 319 1 1 319 3 1 319 19 1 306 24 0 1 300 0 1 312 1 1 312 3 1 312 19 1 300 22.1184 0 1 276 0 1 288 1 1 288 3 1 288 19 1 276 16 0 1 200 0 1 208 1 1 208 3 1 208 19 1 200 12.25 0 0 306 0 0 319 1 0 319 3 0 319 19 0 306 12 0 0 300 0 0 312 1 0 312 3 0 312 19 0 300 11.0592 0 0 276 0 0 288 1 0 288 3 0 288 19 0 276 8 0 0 200 0 0 208 1 0 208 3 0 208 19 0 200 prescaler ln sysclk 4000000 ------------------------ - 1 ln2 -------- 1 ? ? = divider sysclk 2 prescaler 1 + ?? 20000 ? --------------------------------------------------------------------- - = prescaler ln 24000000 4000000 -------------------------- 1 ln2 -------- 1 ? ? 1.585 =1 ? = divider 24000000 2 11 + ?? 20000 ? --------------------------------------------- 3 0 0 ==
c8051f54x 174 rev. 1.1 19.3. lin master mode operation the master node is responsible for the scheduling of messages and sends the header of each frame con- taining the synch break fiel d, synch field, and identifier fiel d. the steps to schedule a mes- sage transmission or reception are listed below. 1. load the 6-bit identifier into the lin0id register. 2. load the data length into the lin0size register. se t the value to the number of data bytes or "1111b" if the data length should be decoded from the identifier. also, set the checksum type, classic or enhanced, in the same lin0size register. 3. set the data direction by setting the txrx bit (l in0ctrl.5). set the bit to 1 to perform a master transmit operation, or set the bit to 0 to perform a master receive operation. 4. if performing a master transmit operation, load the data bytes to transmit into the data buffer (lin0dt1 to lin0dt8). 5. set the streq bit (lin0ctrl.0) to start the mess age transfer. the lin cont roller will schedule the message frame and request an interrupt if the message transfer is successfully co mpleted or if an error has occurred. this code segment shows the procedure to schedule a message in a transmission operation: lin0adr = 0x08; // point to lin0ctrl lin0dat |= 0x20; // select to transmit data lin0adr = 0x0e; // point to lin0id lin0dat = 0x11; // load the id, in this example 0x11 lin0adr = 0x0b; // point to lin0size lin0dat = ( lin0dat & 0xf0 ) | 0x08; // load the size with 8 lin0adr = 0x00; // point to data buffer first byte for (i=0; i<8; i++) { lin0dat = i + 0x41; // load the buffer with ?a?, ?b?, ... lin0adr++; // increment the address to the next buffer } lin0adr = 0x08; // point to lin0ctrl lin0dat = 0x01; // start request the application should perform the following steps when an interrupt is requested. table 19.3. autobaud parameters examples system clock (mhz) prescaler divider 25 1 312 24.5 1 306 24 1 300 22.1184 1 276 16 1 200 12.25 0 306 12 0 300 11.0592 0 276 8 0 200
rev. 1.1 175 c8051f54x 1. check the done bit (lin0st.0) and the error bit (lin0st.2). 2. if performing a master receive operation and the transfer was successful, read the received data from the data buffer. 3. if the transfer was not succe ssful, check the error register to determine the kind of error. further error handling has to be done by the application. 4. set the rstint (lin0ctrl.3) and rsterr bits (l in0ctrl.2) to reset the interrupt request and the error flags. 19.4. lin slave mode operation when the device is configured for slave mode operati on, it must wait for a command from a master node. access from the firmware to the data buffer and id re gisters of the lin controller is only possible when a data request is pending (dtreq bit (lin0st.4) is 1) and also when the lin bus is not active (active bit (lin0st.7) is set to 0). the lin controller in slave mode detects the header of the message frame sent by the lin master. if slave synchronization is enabled (autobaud), the slave synchron izes its internal bit time to the master bit time. the lin controller configured for sl ave mode will generat ed an interrupt in on e of three situations: 1. after the reception of the identifier field 2. when an error is detected 3. when the message transfer is completed. the application should perform the following steps when an interrupt is detected: 1. check the status of the dtreq bit (lin0st.4). this bit is set when the identifier field has been received. 2. if dtreq (lin0st.4) is set, read the identifier from lin0id and process it. if dtreq (lin0st.4) is not set, continue to step 7. 3. set the txrx bit (lin0ctrl.5) to 1 if the current frame is a transmit operation for the slave and set to 0 if the current frame is a receive operation for the slave. 4. load the data length into lin0size. 5. for a slave transmit operation, load the data to transmit into the data buffer. 6. set the dtack bit (lin0ctrl.4). continue to step 10. 7. if dtreq (lin0st.4) is not set, ch eck the done bit (lin0st.0). the tr ansmission was successful if the done bit is set. 8. if the transmission was su ccessful and the current frame was a receive operation for the slave, load the received data bytes from the data buffer. 9. if the transmission was not successful, check lin0e rr to determine the nature of the error. further error handling has to be done by the application. 10.set the rstint (lin0ctrl.3) a nd rsterr bits (lin0ctrl.2) to re set the interrupt request and the error flags. in addition to these steps, the app lication should be aware of the following: 1. if the current frame is a transmit operation for the slave, steps 1 through 5 must be completed during the in-frame response space. if it is not comp leted in time, a timeout will be detected by the master. 2. if the current frame is a receive operation for the slav e, steps 1 through 5 have to be finished until the reception of the first byte after the identifier field. otherwise, the internal receive buffer of the lin controller will be overwritten and a timeout er ror will be detected in the lin controller.
c8051f54x 176 rev. 1.1 3. the lin controller does not directly support lin version 1.3 extended frames. if the application detects an unknown identifier (e.g. extended identifier), it has to write a 1 to the stop bit (lin0ctrl.7) instead of setting the dtack (lin0ctrl.4) bit. at that ti me, steps 2 through 5 can then be skipped. in this situation, the lin controller stops the processing of lin communication unt il the next sync break is received. 4. changing the configuration of t he checksum during a transaction will cause the in terface to reset and the transaction to be lost. to prevent this, the checksum should not be configured while a transaction is in progress. the same applies to changes in the lin interface mode from slave mode to master mode and from master mode to slave mode. 19.5. sleep mode and wake-up to reduce the system?s power consumption, the li n protocol specification defines a sleep mode. the message used to broadcast a sleep mode request mu st be transmitted by the lin master application in the same way as a normal transmit message. the lin slave application must decode the sleep mode frame from the identifier and data bytes. after that, it has to put the lin slave node into the sleep mode by setting the sleep bit (lin0ctrl.6). if the sleep bit (lin0ctrl.6) of the lin slave application is not set and there is no bus activity for four seconds (specified bus idle timeout), the idltout bit (lin0st.6) is set and an interrupt request is gener- ated. after that the application may assume that the lin bus is in sleep mode and set the sleep bit (lin0ctrl.6). sending a wake-up signal from the master or any slave node terminates the sleep mode of the lin bus. to send a wake-up signal, the application has to set t he wupreq bit (lin0ctrl.1). after successful trans- mission of the wake-up signal, the done bit (lin0st.0) of the master node is set and an interrupt request is generated. the lin slave does not generate an inte rrupt request after successful transmission of the wake-up signal but it generates an interrupt request if the master does not respond to the wake-up signal within 150 milliseconds. in that case, the error bit (lin0st.2) and tout bit (lin0err.2) are set. the application then has to decide whether or not to transmit another wake-up signal. all lin nodes that detect a wake-u p signal will set the wakeup (lin0st.1) and done bits (lin0st.0) and generate an interrupt request. afte r that, the application has to clear the sleep bit (lin0ctrl.6) in the lin slave. 19.6. error det ection and handling the lin controller generates an interr upt request and stops the processing of the current frame if it detects an error. the application has to check the type of erro r by processing lin0err. after that, it has to reset the error register and the error bit (lin0st.2) by wr iting a 1 to the rsterr bit (lin0ctrl.2). starting a new message with the lin controller selected as mast er or sending a wakeup signal with the lin control- ler selected as a master or slave is possible on ly if the error bit (lin0st.2) is set to 0.
rev. 1.1 177 c8051f54x 19.7. lin registers the following special function register s (sfrs) and indirect registers are available for the lin controller. 19.7.1. lin direct access sfr registers definitions sfr address = 0xd3; sfr page = 0x00 sfr address = 0xd2; sfr page = 0x00 sfr definition 19.1. lin0adr: lin0 indir ect address register bit 7 6 5 4 3 2 1 0 name lin0adr[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 lin0adr[7:0] lin indirect address register bits. this register hold an 8-bit address used to indirectly access the lin0 core registers. ta b l e 19.4 lists the lin0 core registers and their indirect addresses. reads and writes to lin0dat will target the regi ster indicated by the lin0adr bits. sfr definition 19.2. lin0dat: lin0 indirect data register bit 7 6 5 4 3 2 1 0 name lin0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 lin0dat[7:0] lin indirect data register bits. when this register is read, it will read the contents of the lin0 core register pointed to by lin0adr. when this register is written, it will write the value to the lin0 core register pointed to by lin0adr.
c8051f54x 178 rev. 1.1 sfr address = 0xc9; sfr page = 0x0f sfr definition 19.3. lin0cf: lin0 control mode register bit 7 6 5 4 3 2 1 0 name linen mode abaud type r/w r/w r/w r r r r r reset 0 1 1 0 0 0 0 0 bit name function 7 linen lin interface enable bit. 0: lin0 is disabled. 1: lin0 is enabled. 6 mode lin mode selection bit. 0: lin0 operates in slave mode. 1: lin0 operates in master mode. 5 abaud lin mode automatic baud rate selection. this bit only has an effect when the mo de bit is configured for slave mode. 0: manual baud rate selection is enabled. 1: automatic baud rate selection is enabled. 4:0 unused read = 00000b; write = don?t care
rev. 1.1 179 c8051f54x 19.7.2. lin indirect access sfr registers definitions table 19.4 lists the 15 indirect registers used to configured and communicate with the lin controller. table 19.4. lin registers* (indirectly addressable) name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lin0dt1 0x00 data1[7:0] lin0dt2 0x01 data2[7:0] lin0dt3 0x02 data3[7:0] lin0dt4 0x03 data4[7:0] lin0dt5 0x04 data5[7:0] lin0dt6 0x05 data67:0] lin0dt7 0x06 data7[7:0] lin0dt8 0x07 data8[7:0] lin0ctrl 0x08 stop(s) sleep(s) txrx dtack(s) rstint rsterr wupreq streq(m) lin0st 0x09 active idltout abort(s ) dtreq(s) linint error wakeup done lin0err 0x0a synch(s) prty(s) tout chk biterr lin0size 0x0b enhchk linsize[3:0] lin0div 0x0c divlsb[7:0] lin0mul 0x0d prescl[1:0] linmul[4:0] div9 lin0id 0x0e id5 id4 id3 id2 id1 id0 *note: these registers are used in both master and slave mode. th e register bits marked with (m) are accessible only in master mode while the register bits marked with (s) ar e accessible only in slave mode. all other registers are accessible in both modes.
c8051f54x 180 rev. 1.1 indirect address: lin0dt1 = 0x00, lin0dt2 = 0x01, lin0dt3 = 0x02, lin0dt4 = 0x03, lin0dt5 = 0x04, lin0dt6 = 0x05, lin0dt7 = 0x06, lin0dt8 = 0x07 lin register definition 19.4. lin0dtn: lin0 data byte n bit 7 6 5 4 3 2 1 0 name datan[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 datan[7:0] lin data byte n. serial data byte that is received or transmitted across the lin interface.
rev. 1.1 181 c8051f54x indirect address = 0x08 lin register definition 19.5. lin0ctrl: lin0 control register bit 7 6 5 4 3 2 1 0 name stop sleep txrx dtack rstint rsterr wupreq streq type w r/w r/w r/w w w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 stop stop communication processing bit. (slave mode only) this bit always reads as 0. 0: no effect. 1: block the processing of lin communica tions until the next sync break signal. 6 sleep sleep mode bit. (slave mode only) 0: wake the device after receiving a wakeup interrupt. 1: put the device into sleep mode after receiving a sleep mode frame or a bus idle timeout. 5 txrx transmit / receive selection bit. 0: current frame is a receive operation. 1: current frame is a transmit operation. 4 dtack data acknowledge bit. (slave mode only) set to 1 after handling a data request interrupt to acknowledge the transfer. the bit will automatically be cleared to 0 by the lin controller. 3 rstint reset interrupt bit. this bit always reads as 0. 0: no effect. 1: reset the linint bit (lin0st.3). 2 rsterr reset error bit. this bit always reads as 0. 0: no effect. 1: reset the error bits in lin0st and lin0err. 1 wupreq wakeup request bit. set to 1 to terminate sleep mode by se nding a wakeup signal. the bit will automati - cally be cleared to 0 by the lin controller. 0 streq start request bit. (master mode only) 1: start a lin transmission. this should be set only after loading the identifier, data length and data buffer if necessary. the bit is reset to 0 upon transmission completion or error detection.
c8051f54x 182 rev. 1.1 indirect address = 0x09 lin register definition 19.6. lin0st: lin0 status register bit 7 6 5 4 3 2 1 0 name active idltout abort dtreq linint error wakeup done type r r r r r r r r reset 0 0 0 0 0 0 0 0 bit name function 7 active lin active i ndicator bit. 0: no transmission activity detected on the lin bus. 1: transmission activity detected on the lin bus. 6 idlt bus idle timeout bit. (slave mode only) 0: the bus has not been idle for four seconds. 1: no bus activity has been detected for four seconds, but the bus is not yet in sleep mode. 5 abort aborted transmission bit. (slave mode only) 0: the current transmission has not been interrupted or stopped. this bit is reset to 0 after receiving a synch br eak that does not in terrupt a pendi ng transmission. 1: new synch break detected before the e nd of the last transmission or the stop bit (lin0ctrl.7) has been set. 4 dtreq data request bit. (slave mode only) 0: data identifier has not been received. 1: data identifier has been received. 3 linint interrupt request bit. 0: an interrupt is not pending. this bi t is cleared by setting rstint (lin0ctrl.3) 1: there is a pending lin0 interrupt. 2 error communication error bit. 0: no error has been detected. this bit is cleared by setting rsterr (lin0ctrl.2) 1: an error has been detected. 1 wakeup wakeup bit. 0: a wakeup signal is not being transmitted and has not been received. 1: a wakeup signal is being transmitted or has been received 0 done transmission complete bit. 0: a transmission is not in progress or has not been started. this bit is cleared at the start of a transmission. 1: the current transm ission is complete.
rev. 1.1 183 c8051f54x indirect address = 0x0a lin register definition 19.7. lin0err: lin0 error register bit 7 6 5 4 3 2 1 0 name synch prty tout chk biterr type r r r r r r r r reset 0 0 0 0 0 0 0 0 bit name function 7:5 unused read = 000b; write = don?t care 4 synch synchronization error bit (slave mode only). 0: no error with the synch field has been detected. 1: edges of the synch field are outside of the maximum tolerance. 3 prty parity error bit (slave mode only). 0: no parity error has been detected. 1: a parity error has been detected. 2 tout timeout error bit. 0: a timeout error has not been detected. 1: a timeout error has been detected. this error is detected whenever one of the fol - lowing conditions is met: ? the master is expecting data from a slave and the slave does not respond. ? the slave is expecting data but no data is transmitted on the bus. ? a frame is not finished within the maximum frame length. ? the application does not set the dtack bit (lin0ctrl.4) or stop bit (lin0ctrl.7) until the end of the reception of the firs t byte after the identifier. 1 chk checksum error bit. 0: checksum error has not been detected. 1: checksum error has been detected. 0 biterr bit transmission error bit. 0: no error in transmission has been detected. 1: the bit value monitored during transmission is different than the bit value sent.
c8051f54x 184 rev. 1.1 indirect address = 0x0b lin register definition 19.8. lin0size: lin0 message size register bit 7 6 5 4 3 2 1 0 name enhchk linsize[3:0] type r/w r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7 enhchk checksum selection bit. 0: use the classic, specif ication 1.3 compliant checksum. checksum covers the data bytes. 1: use the enhanced, specif ication 2.0 compliant checksu m. checksum covers data bytes and protected identifier. 6:4 unused read = 000b; write = don?t care 3:0 linsize[3:0] data field size. 0000: 0 data bytes 0001: 1 data byte 0010: 2 data bytes 0011: 3 data bytes 0100: 4 data bytes 0101: 5 data bytes 0110: 6 data bytes 0111: 7 data bytes 1000: 8 data bytes 1001-1110: reserved 1111: use the id[1:0] bits (lin0id[5: 4]) to determine the data length.
rev. 1.1 185 c8051f54x indirect address = 0x0c indirect address = 0x0d lin register definition 19.9. lin0div: lin0 divider register bit 7 6 5 4 3 2 1 0 name divlsb[3:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 divlsb lin baud rate divider least significant bits. the 8 least significant bits for the baud rate divider. the 9th and most significant bit is the div9 bit (lin0mul.0 ). the valid range for the divider is 200 to 511. lin register definition 19.10. lin0mul: lin0 multiplier register bit 7 6 5 4 3 2 1 0 name prescl[1:0] linmul[4:0] div9 type r/w r/w r/w reset 1 1 1 1 1 1 1 1 bit name function 7:6 prescl[1:0] lin baud rate prescaler bits. these bits are the baud rate prescaler bits. 5:1 linmul[4:0] lin baud rate multiplier bits. these bits are the baud rate multiplier bits. these bits are not used in slave mode. 0 div9 lin baud rate divider most significant bit. the most significant bit of the baud rate divider. the 8 least significant bits are in lin0div. the valid range for the divider is 200 to 511.
c8051f54x 186 rev. 1.1 indirect address = 0x0e lin register definition 19.11. lin0id: lin0 identifier register bit 7 6 5 4 3 2 1 0 name id[5:0] type r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:6 unused read = 00b; write = don?t care. 5:0 id[5:0] lin identifier bits. these bits form the data identifier. if the linsize bits (lin0size[3:0]) are 1111 b, bits id[5:4] are used to determine the data size and are interpreted as follows: 00: 2 bytes 01: 2 bytes 10: 4 bytes 11: 8 bytes
rev. 1.1 187 c8051f54x 20. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatib le with the i2c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonom ously controlling the serial transfer of the data. data can be transferre d at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple mas- ters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and gene ration. a block diagram of the smbus peripheral and the associated sfrs is shown in figure 20.1. figure 20.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n arbitration scl synchronization scl generation (master mode) sda control irq generation
c8051f54x 188 rev. 1.1 20.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including s pecifications), philips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification? version 1.1, sbs implementers forum. 20.2. smbus configuration figure 20.2 shows a typical smbus configuration. th e smbus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus ma y operate at different voltage levels. the bi-direc- tional scl (serial clock) and sda (serial data) lines mu st be connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 20.2. typical smbus configuration 20.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbi tration. it is not necessary to specify one device as the master in a system; any device who transmits a start and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledg ed (ack) with a low sda during a high scl (see figure 20.3). if the receiving devi ce does not ack, the tr ansmitting device will read a nack (not acknowl- edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. vio = 5 v master device slave device 1 slave device 2 vio = 3 v vio = 5 v vio = 3 v sda scl
rev. 1.1 189 c8051f54x all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and direction bit. if the trans- action is a write operation from the master to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to term inate the transaction an d free the bus. figure 20 .3 illustrates a typical smbus transaction. figure 20.3. smbus transaction 20.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or data byte to another device on the bus. a device is a ?receiver? when an address or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is sent by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. 20.3.2. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?20.3.5. scl high (smbus free) timeout? on page 190). in the event that two or more devices attempt to begin a transfer at the same time, an arbitra- tion scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while th e other transmits a low. since the bus is open-drain , the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 20.3.3. clock low extension smbus provides a clock synchronization mechanism, similar to i 2 c, which allows devices with different speed capabilities to coexist on the bus. a clock-low extensio n is used during a transf er in order to allow slower slave devices to communicate with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 20.3.4. scl low timeout if the scl line is held low by a slave device on the bus , no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have detected the timeout condition must reset the communi- cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to reload when scl is high, and allowed to count when sc l is low. with timer 3 enabled and configured to sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop
c8051f54x 190 rev. 1.1 overflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. 20.3.5. scl high (smbus free) timeout the smbus specification stipulates th at if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the smbfte bit in smb0cf is set, the bus will be c onsidered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the st art will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave-only implementation. 20.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con- trol for serial transfers; higher level protocol is dete rmined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as defined by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information smbus interrupts are generated for each data byte or slave address that is transf erred. the point at which the interrupt is generated depends on whether the hard ware is acting as a data transmitter or receiver. when a transmitter (i.e., sending address/data, receiving an ack), this interrupt is generated after the ack cycle so that software may read the received ack val ue; when receiving data (i.e. receiving address/data, sending an ack), this interrupt is generated before the ack cycle so that software may define the outgo- ing ack value. see section 20.5 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus interrupt. th e smb0cn register is described in section 20.4.2; table 20.4 provides a quick smb0cn decoding reference. 20.4.1. smbus conf iguration register the smbus configuration register (smb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options. when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave in terrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer).
rev. 1.1 191 c8051f54x the smbcs1?0 bits select the smbu s clock source, which is used only when operating as a master or when the free timeout detection is enabled. when operating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 20.1. note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uart baud rates simultaneously. timer configuration is covered in section ?23. timers? on page 227. equation 20.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 20.1. when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 20.2. equation 20.2. typical smbus bit rate figure 20.4 shows the typical scl generation described by equation 20.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will ne ver exceed the limits defined by equation equation 20.1. figure 20.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times table 20.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------- ------------------ --------------- == bitrate f clocksourceoverflow 3 ----------------- ----------------- --------------- = scl timer source overflows scl high timeout t low t high
c8051f54x 192 rev. 1.1 meet the smbus specification requirements of 250 ns and 300 ns, respectively. table 20.2 shows the min- imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section ?20. 3.4. scl low timeout? on page 189). the smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count wh en scl is low. the timer 3 interrupt service routine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detecti on can be enabled by setting the smbfte bi t. when this bit is set, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 20.4). table 20.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks *note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgement, the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero.
rev. 1.1 193 c8051f54x sfr address = 0xc1; sfr page = 0x00 sfr definition 20.1. smb0cf: smbus clock/configuration bit 7 6 5 4 3 2 1 0 name ensmb inh busy exthold smbtoe smbfte smbcs[1:0] type r/w r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ensmb smbus enable. this bit enables the smbus interface when set to 1. when enabled, the interface constantly monitors the sda and scl pins. 6 inh smbus slave inhibit. when this bit is set to logic 1, the smbu s does not generate an interrupt when slave events occur. this effectively removes th e smbus slave from the bus. master mode interrupts are not affected. 5 busy smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to ta b l e 20.2 . 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. 3 smbtoe smbus scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. if timer 3 is configured to split mode, only the high byte of the timer is held in reload while scl is high. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus communication. 2 smbfte smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 smbus clock source periods. 1:0 smbcs[1:0] smbus clock source selection. these two bits select the smbus clock sour ce, which is used to generate the smbus bit rate. the selected device should be configured according to equation 20.1 . 00: timer 0 overflow 01: timer 1 overflow 10:timer 2 high byte overflow 11: timer 2 low byte overflow
c8051f54x 194 rev. 1.1 20.4.2. smb0cn control register smb0cn is used to control the interface and to provid e status information (see sfr definition 20.2). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is tr ansmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop has been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas- ter. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardwar e after the start is generated). writing a 1 to sto while in master mode will cause th e interface to generate a stop an d end the current transfer after the next ack cycle. if sto and sta are both set (while in mast er mode), a stop followed by a start will be generated. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received during the last ack cycle. ackrq is set each time a byte is received, indicat- ing that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if so ftware does not write the ack bit before clearing si. sda will reflec t the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave ad dress is not acknowledged, further slave events will be ignored until th e next start is detected. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condi- tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginnin g and end of each transfer, after each byte frame, or when an arbitration is lost; see table 20.3 for more details. important note about the si bit: the smbus interface is st alled while si is set; th us scl is held low, and the bus is stalled until software clears si.
rev. 1.1 195 c8051f54x sfr address = 0xc0; bit-addressable; sfr page =0x00 sfr definition 20.2. smb0cn: smbus control bit 7 6 5 4 3 2 1 0 name master txmode sta sto ackrq arblost ack si type r r r/w r/w r r r/w r/w reset 0 0 0 0 0 0 0 0 bit name description read write 7 master smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. n/a 6 txmode smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. n/a 5 sta smbus start flag. 0: no start or repeated start detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a master, initiates a start or repeated start. 4 sto smbus stop flag. 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pend - ing (if in master mode). 0: no stop condition is transmitted. 1: when configured as a master, causes a stop condition to be transmit - ted after the next ack cycle. cleared by hardware. 3 ackrq smbus acknowledge request. 0: no ack requested 1: ack requested n/a 2 arblost smbus arbitration lost indicator. 0: no arbitration error. 1: arbitration lost n/a 1 ack smbus acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0 si smbus interrupt flag. this bit is set by hardware under the conditions listed in table 15.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. 0: no interrupt pending 1 : interrupt pending 0: clear interrupt, and initi - ate next state machine event. 1: force interrupt.
c8051f54x 196 rev. 1.1 table 20.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master ? a start is generated. ? a stop is generated. ? arbitration is lost. txmode ? start is generated. ? smb0dat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smb0dat is not written before the start of an smbus frame. sta ? a start followed by an address byte is received. ? must be cleared by software. sto ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ackrq ? a byte has been received and an ack response value is needed. ? after each ack cycle. arblost ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low wh ile attempting to generate a stop or repeated start condition. ? sda is sensed low while transmitting a 1 (excluding ack bits). ? each time si is cleared. ack ? the incoming ack value is low ? (acknowledge). ? the incoming ack value is high (not acknowledge). si ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software.
rev. 1.1 197 c8051f54x 20.4.3. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted out msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi- tration, the transition from master transmitter to slave receiver is made with the correct data or address in smb0dat. sfr address = 0xc2; smb0dat = 0x00 20.5. smbus transfer modes the smbus interface may be configured to operate as master and /or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. as a receiver, the interrupt for an ack occurs before the ack. as a transmitter, interrupts occur after the ack. sfr definition 20.3. smb0dat: smbus data bit 7 6 5 4 3 2 1 0 name smb0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 smb0dat[7:0] smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial interface or a byte that has just b een received on the smbus serial interface. the cpu can read from or write to this regi ster whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu shou ld not attempt to access this register.
c8051f54x 198 rev. 1.1 20.5.1. write se quence (master) during a write sequence, an smbus mast er writes data to a slave device. th e master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case th e data direction bit (r/w) will be logic 0 (write). the ma ster then trans- mits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended wh en the sto bit is set and a stop is generated. note that the interface will switch to master rece iver mode if smb0dat is not written fo llowing a master tran smitter interrupt. figure 20.5 shows a typical master write sequence. two transmit data bytes are shown, though any num- ber of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode. figure 20.5. typical master write sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = wri te sla = slave address received by smbus interface transmitted by smbus interface interrupts
rev. 1.1 199 c8051f54x 20.5.2. read sequence (master) during a read sequence, an smbus master reads da ta from a slave device. the master in this transfer will be a transmitter during the address byte, and a receiv er during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case t he data direction bit (r/w) will be lo gic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. an interrupt is generated after each received byte. software must write the ack bit at that time to ack or nack the received byte. writing a 1 to the ack bit generates an ack; writing a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the interface w ill switch to master transmitter mode if smb0dat is written while an active master receiver. figure 20.6 shows a typical master read sequence. two received data bytes are shown, though any number of bytes may be received. no tice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. figure 20.6. typical master read sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts
c8051f54x 200 rev. 1.1 20.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direc- tion bit (write in this case) is received. upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if the received slave address is igno red, slave interrupts will be inhibite d until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. software must write the ack bit at that time to ac k or nack the received byte. the interface exits slav e receiver mode after receivin g a stop. note that the interface will switch to slave transmitter mode if smb0da t is written while an active slave receiv er. figure 20.7 shows a typical slave write sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur before the ack in this mode. figure 20.7. typical slave write sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = wri te sla = slave address received by smbus interface transmitted by smbus interface interrupts
rev. 1.1 201 c8051f54x 20.5.4. read se quence (slave) during a read sequence, an smbus mast er reads data from a slave device. the slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. the interrupt will occur after the ack cycle. if the received slave address is igno red, slave interrupts will be inhibite d until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are transmitted. if the received slave address is acknowledged, data should be wr itten to smb0dat to be transmitted. the interface enters slave transmitter mode, and transmits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bi t is an ack, smb0dat shou ld be written with the next data byte. if the acknowledge bit is a nack, smb0 dat should not be written to before si is cleared (note: an error condition may be generated if smb0dat is written following a received nack while in slave transmitter mode). the interface exits slave tran smitter mode afte r receiving a stop. note that the interface will switch to slave receiv er mode if smb0dat is not written following a slave transmitter inter- rupt. figure 20.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of bytes may be transmitted. notice that a ll of the ?data byte transferred? interrupts occur after the ack cycle in this mode. figure 20.8. typical slave read sequence 20.6. smbus status decoding the current smbus status can be easily decoded us ing the smb0cn register. in the tables, status ? vector refers to the four upper bits of smb0 cn: master, txmode, sta, and sto. the shown response options are only the typica l responses; application-specific procedures are allowed as long as they conform to the smbus specification. highlighted responses are allowed by hardware but do not con- form to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts
c8051f54x 202 rev. 1.1 table 20.4. smbus status decoding mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener - ated. load slave address + r/w into smb0dat. 0 0 x 1100 1100 0 0 0 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 0 1 x ? 0 0 1 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 0 0 x 1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 1 1 x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 1000 send nack to indicate last byte, and send stop. 0 1 0 ? send nack to indicate last byte, and send stop followed by start. 1 1 0 1110 send ack followed by repeated start. 1 0 1 1110 send nack to indicate last byte, and send repeated start. 1 0 0 1110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas - ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100
rev. 1.1 203 c8051f54x slave transmitter 0100 0 0 0 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 0 0 1 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 0 1 x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 0 0 x ? slave receiver 0010 1 0 x a slave address + r/w was received; ack requested. if write, acknowledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? 1 1 x lost arbitration as master; slave address + r/w received; ack requested. if write, acknowledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? reschedule failed transfer; nack received address. 1 0 0 1110 0001 0 0 x a stop was detected while addressed as a slave trans - mitter or slave receiver. clear sto. 0 0 x ? 1 1 x lost arbitration while attempt - ing a stop. no action required (transfer complete/aborted). 0 0 0 ? 0000 1 0 x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 0000 nack received byte. 0 0 0 ? table 20.4. smbus status decoding mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
c8051f54x 204 rev. 1.1 bus error condition 0010 0 1 x lost arbitration while attempt - ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 1 1 x lost arbitration while transmit - ting a data byte as master. abort failed transfer. 0 0 0 ? reschedule failed transfer. 1 0 0 1110 table 20.4. smbus status decoding mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
rev. 1.1 205 c8051f54x 21. uart0 uart0 is an asynchronous, full duplex serial port offeri ng a variety of data formatting options. a dedicated baud rate generator with a 16-bit timer and select able prescaler is included, which can generate a wide range of baud rates (details in section ?21.1. baud rate generator? on page 205). a received data fifo allows uart0 to receive up to three data bytes before data is lost and an overflow occurs. uart0 has six associated sfrs. three are used for the baud rate generator (sbcon0, sbrlh0, and sbrll0), two are used for data formatting, control, and status functions (scon0, smod0), and one is used to send and receive data (sbuf0). the single sbuf0 location provides access to both the transmit holding register and the receive fifo. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the first byte of the receive fifo; it is not possible to read data from the transmit holding register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). if additional bytes are available in the receive fifo, the ri0 bit cannot be cleared by software. figure 21.1. uart0 block diagram 21.1. baud rate generator the uart0 baud rate is generated by a dedicated 16-bi t timer which runs from the controller?s core clock (sysclk) and has prescaler options of 1, 4, 12, or 48. the timer and prescaler options combined allow for a wide selection of baud rates over many clock frequencies. the baud rate generator is configured using th ree registers: sbcon0, sbrlh0, and sbrll0. the uart0 baud rate generator control register (sbcon0, sfr definition 21.4) enables or disables the baud rate generator and selects the prescaler value for the timer. the baud rate generator must be enabled for uart0 to function. registers sbrlh0 and sbrll0 contain a 16-bit reload value for the dedi- cated 16-bit timer. the internal timer counts up from the reload value on every clock tick. on timer over- flows (0xffff to 0x0000), the timer is reloaded. the baud rate for uart0 is defined in equation 21.1, where ?brg clock? is the baud rate generator?s sele cted clock source. for reliable uart operation, it is recommended that the uart baud rate is not configured for b aud rates faster than sysclk/16. sbuf0 tx holding register rx fifo (3 deep) tx logic rx logic write to sbuf0 read of sbuf0 tx0 rx0 smod0 mce0 s0pt1 s0pt0 pe0 s0dl1 s0dl0 xbe0 sbl0 data formatting scon0 ovr0 perr0 thre0 ren0 tbx0 rbx0 ti0 ri0 control / status uart0 interrupt timer (16-bit) pre-scaler (1, 4, 12, 48) sysclk sbrlh0 sbrll0 overflow sbcon0 sb0run sb0ps1 sb0ps0 en baud rate generator
c8051f54x 206 rev. 1.1 equation 21.1. uart0 baud rate a quick reference for typical baud rates and clock frequencies is given in table 21.1. table 21.1. baud rate generator settings for standard baud rates target baud rate (bps) actual baud rate (bps) baud rate error oscillator divide factor sb0ps[1:0] (prescaler bits) reload value in sbrlh0:sbrll0 sysclk = 48 230400 230769 0.16% 208 11 0xff98 115200 115385 0.16% 416 11 0xff30 57600 57554 0.08% 834 11 0xfe5f 28800 28812 0.04% 1666 11 0xfcbf 14400 14397 0.02% 3334 11 0xf97d 9600 9600 0.00% 5000 11 0xf63c 2400 2400 0.00% 20000 11 0xd8f0 1200 1200 0.00% 40000 11 0xb1e0 sysclk = 24 230400 230769 0.16% 104 11 0xffcc 115200 115385 0.16% 208 11 0xff98 57600 57692 0.16% 416 11 0xff30 28800 28777 0.08% 834 11 0xfe5f 14400 14406 0.04% 1666 11 0xfcbf 9600 9600 0.00% 2500 11 0xfb1e 2400 2400 0.00% 10000 11 0xec78 1200 1200 0.00% 20000 11 0xd8f0 sysclk = 12 230400 230769 0.16% 52 11 0xffe6 115200 115385 0.16% 104 11 0xffcc 57600 57692 0.16% 208 11 0xff98 28800 28846 0.16% 416 11 0xff30 14400 14388 0.08% 834 11 0xfe5f 9600 9600 0.00% 1250 11 0xfd8f 2400 2400 0.00% 5000 11 0xf63c 1200 1200 0.00% 10000 11 0xec78 baud rate sysclk 65536 (sbrlh0:sbrll0) ? ?? ------------------------------------------------------------------------------ x 1 2 -- - x 1 prescaler ------------------------ - =
rev. 1.1 207 c8051f54x 21.2. data format uart0 has a number of available options for data format ting. data transfers begin with a start bit (logic low), followed by the data bits (sent lsb-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). the data length is variable be tween 5 and 8 bits. a parity bit can be appended to the data, and automatically generated and detected by hardware for even, odd, mark, or space parity. the stop bit length is selectable between 1 and 2 bit times, and a multi-processor communication mode is available for implementing networked uart buses. all of the dat a formatting options can be configured using the smod0 register, shown in sfr definition 21.2. figu re 21.2 shows the timing for a uart0 transaction without parity or an extra bit enabled. figure 21.3 sh ows the timing for a uart0 transaction with parity enabled (pe0 = 1). figure 21.4 is an example of a uart0 transaction when the extra bit is enabled (xbe0 = 1). note that the extra bit feature is not ava ilable when parity is enabled, and the second stop bit is only an option for data lengths of 6, 7, or 8 bits. figure 21.2. uart0 timing without parity or extra bit figure 21.3. uart0 timing with parity figure 21.4. uart0 timing with extra bit d 1 d 0 d n-2 d n-1 start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional (6,7,8 bit data) d 1 d 0 d n-2 d n-1 parity start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional (6,7,8 bit data) d 1 d 0 d n-2 d n-1 extra start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional (6,7,8 bit data)
c8051f54x 208 rev. 1.1 21.3. configurat ion and operation uart0 provides standard asynchronous, full duplex communication. it can operate in a point-to-point serial communications application, or as a node on a mult i-processor serial interface. to operate in a point- to-point application, where there are only two devices on the serial bus, the mce0 bit in smod0 should be cleared to 0. for o peration as part of a mult i-processor communications bu s, the mce0 and xbe0 bits should both be set to 1. in both types of applicatio ns, data is transmitted from the microcontroller on the tx0 pin, and received on the rx0 pin. the tx0 and rx0 pins are configured using the crossbar and the port i/o registers, as detailed in section ?18. port input/output? on page 147. in typical uart communications, the transmit (tx) outp ut of one device is connec ted to the receive (rx) input of the other device, either directly or th rough a bus transceiver, as shown in figure 21.5. figure 21.5. typical uart interconnect diagram 21.3.1. data transmission data transmission is double-buffered and begins when software writes a data byte to the sbuf0 register. writing to sbuf0 places data in the transmit holdin g register, and the transmit holding register empty flag (thre0) will be cleared to ?0?. if the uart?s shift register is empty (i.e. no tran smission in progress), the data will be placed in the transmit holding regist er until the curren t transmission is complete. the ti0 transmit interrupt flag (scon0.1) will be set at the end of any transmission (the b eginning of the stop-bit time). if enabled, an interrup t will occur when ti0 is set. if the extra bit function is enabled (xbe0 = ?1?) and the parity function is disabled (pe0 = ?0?), the value of the tbx0 (scon0.3) bit will be sent in the extra bit position. when the pari ty function is enabled (pe0 = 1), hardware will generate the parity bit according to the selected parity type (s elected with s0pt[1:0]), and append it to the data field. note: when parity is enabled, the extra bit function is not available. 21.3.2. data reception data reception can begin any time after the ren0 receiv e enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be stored in the receive fifo if the following condit ions are met: the receive fifo (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. in the event that the receive fifo is full, the incoming byte will be lost, and a receive fi fo overrun error will be generated (ovr0 in register scon0 will be set to logic 1). if the stop bit(s) were lo gic 0, the incoming data will not be stored in the receive fifo. if the reception conditions are met, the data is stored in the receive fifo, and the ri0 flag will be set. note: when mce0 = 1, ri0 will only be set if the extra bit was equal to 1. data can be read from the receive fifo by reading the sbuf0 register. the sbuf0 register represents the oldest byte in the fifo. after sbuf0 is read, the next byte in the fifo is immediately loaded into sbuf0, and space is made available in the fifo for another incomi ng byte. if enabled, an in terrupt will occur when ri0 is set. ri0 can only be cleared to ?0? by software wh en there is no more information in the fifo. the rec- ommended procedure to empty the fifo contents is: or rs-232 c8051fxxx rs-232 level translator tx rx c8051fxxx rx tx mcu rx tx pc com port
rev. 1.1 209 c8051f54x 1. clear ri0 to 0. 2. read sbuf0. 3. check ri0, and repeat at step 1 if ri0 is set to 1. if the extra bit function is en abled (xbe0 = 1) and the parity function is disabled (pe0 = 0), the extra bit for the oldest byte in the fifo can be read from the rbx0 bit (scon0.2). if the extra bit function is not enabled, the value of the stop bit for the oldest fifo byte will be presen ted in rbx0. when the parity func- tion is enabled (pe0 = 1) , hardware will check the re ceived parity bit against th e selected parity type (selected with s0pt[1:0]) wh en receiving data. if a byte with parity error is rece ived, the perr0 flag will be set to 1. this flag must be cleared by software. note: when parity is enabled, the extra bit function is not available. 21.3.3. mult iprocessor communications uart0 supports multiprocessor communication between a master processor and one or more slave pro- cessors by special use of the extra data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target (s). an address byte differs from a data byte in that its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0. setting the mce0 bit (smod0.7) of a slave processor c onfigures its uart such that when a stop bit is received, the uart will generate an interrupt only if the extra bit is logic 1 (rbx0 = 1) signifying an address byte has been rece ived. in the uart interr upt handler, software w ill compare the received address with the slave's own assigned address. if the addres ses match, the slave will clear its mce0 bit to enable interrupts on the reception of the following da ta byte(s). slaves that we ren't addressed leave their mce0 bits set and do not generate interrupts on the rece ption of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce0 bit to ignore all trans- missions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). figure 21.6. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
c8051f54x 210 rev. 1.1 sfr address = 0x98; bit-addressable; sfr page = 0x00 sfr definition 21.1. scon0: serial port 0 control bit 7 6 5 4 3 2 1 0 name ovr0 perr0 thre0 ren0 tbx0 rbx0 ti0 ri0 type r/w r/w r r/w r/w r/w r/w r/w reset 0 0 1 0 0 0 0 0 bit name function 7 ovr0 receive fifo overrun flag. 0: receive fifo overrun has not occurred 1: receive fifo overrun has occurred; a received character has been discarded due to a full fifo. 6 perr0 parity error flag. when parity is enabled, this bit indicates that a parity error has occurred. it is set to 1 when the parity of the oldest byte in the fi fo does not match the selected parity type. 0: parity error has not occurred 1: parity error has occurred. this bit must be cleared by software. 5 thre0 transmit holding register empty flag. 0: transmit holding register not empty?do not write to sbuf0. 1: transmit holding register empt y?it is safe to write to sbuf0. 4 ren0 receive enable. this bit enables/disables the uart receiv er. when disabled, bytes can still be read from the receive fifo. 0: uart1 reception disabled. 1: uart1 reception enabled. 3 tbx0 extra transmission bit. the logic level of this bit will be assigned to the extra transmission bit when xbe0 is set to 1. this bit is not used when parity is enabled. 2 rbx0 extra receive bit. rbx0 is assigned the va lue of the extra bit when xbe1 is set to 1. if xbe1 is cleared to 0, rbx1 will be assigned the logic level of th e first stop bit. this bit is not valid when parity is enabled. 1 ti0 transmit interrupt flag. set to a 1 by hardware after data has been transmitted, at the beginning of the stop bit. when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. 0 ri0 receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 in terrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by soft-ware. note that ri0 will remain set to ?1? as long as there is data still in the uart fifo. after the last byte has been shifted from the fifo to sbuf0, ri0 can be cleared.
rev. 1.1 211 c8051f54x sfr address = 0xa9; sfr page = 0x00 sfr definition 21.2. smod0: serial port 0 control bit 7 6 5 4 3 2 1 0 name mce0 s0pt[1:0] pe0 s0dl[1:0] xbe0 sbl0 type r/w r/w r r/w r/w r/w r/w r/w reset 0 0 0 0 1 1 0 0 bit name function 7 mce0 multiprocessor comm unication enable. 0: ri0 will be activate d if stop bit(s) are 1. 1: ri0 will be activated if stop bit(s) and ex tra bit are 1. extra bit must be enabled using xbe0. 6:5 s0pt[1:0] parity type select bits. 00: odd parity 01: even parity 10: mark parity 11: space parity. 4 pe0 parity enable. this bit enables hardware parity generation and checking. the parity type is selected by bits s0pt[1:0] when parity is enabled. 0: hardware parity is disabled. 1: hardware parity is enabled. 3:2 s0dl[1:0] data length. 00: 5-bit data 01: 6-bit data 10: 7-bit data 11: 8-bit data 1 xbe0 extra bit enable. when enabled, the valu e of tbx0 will be app ended to the data field 0: extra bit is disabled. 1: extra bit is enabled. 0 sbl0 stop bit length. 0: short?stop bit is active for one bit time 1: long?stop bit is active for two bit times (dat a length = 6, 7, or 8 bits), or 1.5 bit times (data length = 5 bits).
c8051f54x 212 rev. 1.1 sfr address = 0x99; sfr page = 0x00 sfr address = 0xab; sfr page = 0x0f sfr definition 21.3. sbuf0: serial (uart0) port data buffer bit 7 6 5 4 3 2 1 0 name sbuf0[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sbuf0[7:0] serial data buffer bits 7?0 (msb?lsb). this sfr accesses two registers; a transmit shift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the contents of the receive latch. sfr definition 21.4. sbcon0: uart0 baud rate generator control bit 7 6 5 4 3 2 1 0 name reserved sb0run reserved reserved reserved reserved sb0ps[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 reserved read = 0b; must write 0b; 6 sb0run baud rate generator enable. 0: baud rate generator disabl ed. uart0 will not function. 1: baud rate generator enabled. 5:2 reserved read = 0000b; must write = 0000b; 1:0 sb0ps[1:0] baud rate prescaler select. 00: prescaler = 12. 01: prescaler = 4. 10: prescaler = 48. 11: prescaler = 1.
rev. 1.1 213 c8051f54x sfr address = 0xad ; sfr page = 0x0f sfr address = 0xac ; sfr page = 0x0f sfr definition 21.5. sbrlh0: uart0 baud rate generator reload high byte bit 7 6 5 4 3 2 1 0 name sbrlh0[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sbrlh0[7:0] high byte of reload value fo r uart0 baud rate generator. this value is loaded into the high byte of the uart0 baud rate generator when the counter overflows from 0xffff to 0x0000. sfr definition 21.6. sbrll0: uart0 baud rate generator reload low byte bit 7 6 5 4 3 2 1 0 name sbrll0[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sbrll0[7:0] low byte of reload value fo r uart0 baud rate generator. this value is loaded into the low byte of the uart0 baud rate generator when the counter overflows from 0xffff to 0x0000.
c8051f54x 214 rev. 1.1 22. enhanced serial pe ripheral interface (spi0) the enhanced serial peripheral interface (spi0) prov ides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave devi ce in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single spi bus. the slav e-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen- eral purpose port i/o pins can be used to se lect multiple slave dev ices in master mode. figure 22.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien
rev. 1.1 215 c8051f54x 22.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 22.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat- ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 22.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output fr om a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat- ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 22.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen- erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 22.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possible modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave device, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on th e bus in 3-wire mode. this is intended for point-to- point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of the nss signal disabl es the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 determ ines what logic level the nss pi n will output. this configuration should only be used when operating spi0 as a master device. see figure 22.2, figure 22.3, and figure 22.4 for typi cal connection diagrams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?18. port input/output? on page 147 for general purpose port i/o and crossbar information.
c8051f54x 216 rev. 1.1 22.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spif (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift regist er to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another mast er is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) ar e set to 0 to disable the spi master device, and a mode fault is gene rated (modf, spi0cn.5 = 1). mode fault w ill generate an interrupt if enabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master syst ems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas- ter mode, slave devices can be addressed individua lly (if needed) using general-purpose i/o pins. figure 22.2 shows a connection diagram between two master devices in multiple-mas ter mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 22.3 shows a connection diagram between a master devic e in 3-wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0c n.3) = 1. in this mode, nss is configured as an output pin, and can be used as a sl ave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit n ssmd0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 22.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices.
rev. 1.1 217 c8051f54x figure 22.2. multiple-master mode connection diagram figure 22.3. 3-wire single master and 3-wire single slave mode connection diagram figure 22.4. 4-wire single master mode and 4-wire slave mode connection diagram master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss
c8051f54x 218 rev. 1.1 22.3. spi0 slave mode operation when spi0 is enabled and not configured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig- nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted through the shift reg- ister, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabled when nss is logic 0, and disabled when nss is logic 1. th e bit counter is reset on a falling ed ge of nss. note that the nss sig- nal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 22.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0c n.3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 22.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 22.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. 1. the spi interrupt flag, spif (spi0cn.7) is set to logi c 1 at the end of each byte transfer. this flag can occur in all spi0 modes. 2. the write collision flag, wcol (spi 0cn.6) is set to logic 1 if a wr ite to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the tr ansmit buffer will not be writte n.this flag can oc cur in all spi0 modes. 3. the mode fault flag modf (spi0cn.5) is set to logic 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disable spi0 an d allow another master device to access the bus. 4. the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the rece ive buffer still holds an unread byte from a prev ious transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost.
rev. 1.1 219 c8051f54x 22.5. serial clock phase and polarity four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0c fg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0 cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 22.5. for slave mode, the clock and data relationships are shown in figure 22.6 and figure 22.7. ckpha must be set to 0 on both the master and slave spi when communicating between two of the following devices: c8051f04x, c8051f06x, c8051f12x, c8051f31x, c8051f32x, and c8051f33x. the spi0 clock rate register (spi0c kr) as shown in sfr definition 22.3 controls the master mode serial clock frequency. this register is ignored when operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the s ystem clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial input data synchronously with the slave?s system clock. figure 22.5. master mode data/clock timing sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode)
c8051f54x 220 rev. 1.1 figure 22.6. slave mode data/clock timing (ckpha = 0) figure 22.7. slave mode data/clock timing (ckpha = 1) 22.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data register, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi
rev. 1.1 221 c8051f54x sfr address = 0xa1; sfr page = 0x00 sfr definition 22.1. spi0cfg: spi0 configuration bit 7 6 5 4 3 2 1 0 name spibsy msten ckpha ckpol slvsel nssin srmt rxbmt type r r/w r/w r/w r r r r reset 0 0 0 0 0 1 1 1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4 ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but rather a de-glitched ver - sion of the pin input. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. 1 srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all data has been tran sferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer . it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the re ceive buffer has been read and contains no new information. if there is new informatio n available in the receive buffer that has not been read, this bit w ill return to logic 0. rxbm t = 1 when in master mode. note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 22.1 for timing parameters.
c8051f54x 222 rev. 1.1 sfr address = 0xf8; bit-addressable; sfr page = 0x00 sfr definition 22.2. spi0cn: spi0 control bit 7 6 5 4 3 2 1 0 name spif wcol modf rxovrn nssmd[1:0] txbmt spien type r/w r/w r/w r/w r/w r r/w reset 0 0 0 0 0 1 1 0 bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt service rou - tine. this bit is not automatically cleare d by hardware. it must be cleared by soft - ware. 6 wcol write collision flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) to indicate a write to the spi0 data register was attempted while a data transfer was in progress. it must be cleared by software. 5 modf mode fault flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when a mas - ter mode collision is detect ed (nss is low, msten = 1, and nssmd[1:0] = 01). this bit is not automatically cleared by hardware. it must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when the receive buffer still holds unread data from a previous transf er and the last bit of the current transfer is shifted in to the spi0 shift register. this bit is not automatically cleared by hardware. it must be cleared by software. 3:2 nssmd[1:0] slave select mode. selects between the following nss operation modes: (see section 22.2 and section 22.3 ). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efault). nss is an input to the device. 1x: 4-wire single-master mode. nss sign al is mapped as an output from the device and will assume the value of nssmd0. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new da ta has been written to the transmit buffer. when data in the transmit buff er is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled.
rev. 1.1 223 c8051f54x sfr address = 0xa2; sfr page = 0x00 sfr address = 0xa3; sfr page = 0x00 sfr definition 22.3. spi0ckr: spi0 clock rate bit 7 6 5 4 3 2 1 0 name scr[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 scr[7:0] spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided ver - sion of the system clock, and is given in the following equa tion, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, sfr definition 22.4. spi0dat: spi0 data bit 7 6 5 4 3 2 1 0 name spi0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 spi0dat[7:0] spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0dat places the data into the transmi t buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. f sck sysclk 2 x spi0ckr[7:0] 1 + ?? --------------------------------------------------------------- - = f sck 2000000 2 x 41 + ?? ----------------------------- - = f sck 200 khz =
c8051f54x 224 rev. 1.1 figure 22.8. spi master timing (ckpha = 0) figure 22.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis
rev. 1.1 225 c8051f54x figure 22.10. spi slave timing (ckpha = 0) figure 22.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz
c8051f54x 226 rev. 1.1 table 22.1. spi slave timing parameters parameter description min max units master mode timing * (see figure 22.8 and figure 22.9 ) t mckh sck high time 1 x t sysclk ? ns t mckl sck low time 1 x t sysclk ? ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing * (see figure 22.10 and figure 22.11 ) t se nss falling to first sck edge 2 x t sysclk ? ns t sd last sck edge to nss rising 2 x t sysclk ? ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ? ns t ckl sck low time 5 x t sysclk ? ns t sis mosi valid to sck sample edge 2 x t sysclk ? ns t sih sck sample edge to mosi change 2 x t sysclk ? ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change ? (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns *note: t sysclk is equal to one period of the device system clock (sysclk).
rev. 1.1 227 c8051f54x 23. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer fo r use with the adc, smbus, or for general purpose use. these timers can be used to measure time inte rvals, count external even ts and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timer 2 and timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. timers 0 and 1 may be clocked by one of five sour ces, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1 ? sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 23.1 for pre-scaled clock selection).timer 0/1 may then be configured to use this pre- scaled clock signal or the system clock. timer 2 and timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counte rs. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre- quency of up to one-fourth the system clock frequency can be counted. the input signal need not be peri- odic, but it should be held at a gi ven level for at least two full system cl ock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes timer 2 modes timer 3 modes 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with ? auto-reload two 8-bit timers with auto-reload two 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
c8051f54x 228 rev. 1.1 sfr address = 0x8e; sfr page = all pages sfr definition 23.1. ckcon: clock control bit 7 6 5 4 3 2 1 0 name t3mh t3ml t2mh t2ml t1m t0m sca[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defin ed by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6 t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. selects the clock supplie d to the lower 8-bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5 t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defin ed by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4 t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supp lied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3 t1 timer 1 clock select. selects the clock source supplied to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale bits sca[1:0]. 1: timer 1 uses the system clock. 2 t0 timer 0 clock select. selects the clock source supplied to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defined by the prescale bits sca[1:0]. 1: counter/timer 0 uses the system clock. 1:0 sca[1:0] timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (synchronized with the system clock)
rev. 1.1 229 c8051f54x 23.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer control register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis- ter (section ?13.2. interrupt register descriptions? on page 108); timer 1 interrupts can be enabled by set- ting the et1 bit in the ie register (section ?13.2. interrupt register descriptions? on page 108). both counter/timers operate in one of four primary m odes selected by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 23.1.1. mode 0: 13 -bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 (tcon.5) is set and an interrupt will occur if timer 0 interrupts are enabled. the c/t0 bit (tmod.2) selects the counter/timer's cloc k source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?18.3. priority crossbar decoder? on page 150 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by th e t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0 m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 23.1). setting the tr0 bit (tcon.4) enables the timer when ei ther gate0 (tmod.3) is logic 0 or the input signal int0 is active as defined by bit in0pl in register it01 cf (see sfr definition 13.7). setting gate0 to 1 allows the timer to be controlled by the external input signal int0 (see section ?13.2. interrupt register descriptions? on page 108), fac ilitating pulse width measurements. setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal int1 is used with timer 1; the int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 13.7). tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care
c8051f54x 230 rev. 1.1 figure 23.1. t0 mode 0 block diagram 23.1.2. mode 1: 16 -bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun- ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 23.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8- bit counter/timers with auto matic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer overflow flag tf0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an in terrupt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired va lue before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal int0 is active as defined by bit in0pl in register it01cf (see section ?13.3. external interrupts int0 and int1? on page 115 for details on the external input signals int0 and int1 ). tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie 1 it1 ie 0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in 0pl xor
rev. 1.1 231 c8051f54x figure 23.2. t0 mode 2 block diagram 23.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the coun- ter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an ex ternal input signal as its timebase. the th0 register is restricted to a timer function so urced by the system clock or presca led clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 ov erflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operat ing in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and/or uart, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set- tings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
c8051f54x 232 rev. 1.1 figure 23.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 1.1 233 c8051f54x sfr address = 0x88; bit-addres sable; sfr page = all pages sfr definition 23.2. tcon: timer control bit 7 6 5 4 3 2 1 0 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 6 tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 4 tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3 ie1 external interrupt 1. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2 it1 interrupt 1 type select. this bit selects whether the configured int1 interrupt will be edge or level sensitive. int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 13.7 ). 0: int1 is level triggered. 1: int1 is edge triggered. 1 ie0 external interrupt 0. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0 it0 interrupt 0 type select. this bit selects whether the configured int0 interrupt will be edge or level sensitive. int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 13.7 ). 0: int0 is level triggered. 1: int0 is edge triggered.
c8051f54x 234 rev. 1.1 sfr address = 0x89; sfr page = all pages sfr definition 23.3. tmod: timer mode bit 7 6 5 4 3 2 1 0 name gate1 c/t1 t1m[1:0] gate0 c/t0 t0m[1:0] type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in register it01cf (see sfr definition 13.7 ). 6 c/t1 counter/timer 1 select. 0: timer: timer 1 incremented by clock defined by t1m bit in register ckcon. 1: counter: timer 1 incremented by high-to-low transitions on external pin (t1). 5:4 t1m[1:0] timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3 gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in register it01cf (see sfr definition 13.7 ). 2 c/t0 counter/timer 0 select. 0: timer: timer 0 incremented by clock defined by t0m bit in register ckcon. 1: counter: timer 0 incremented by high-to-low transitions on external pin (t0). 1:0 t0m[1:0] timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers
rev. 1.1 235 c8051f54x sfr address = 0x8a; sfr page = all pages sfr address = 0x8b; sfr page = all pages sfr definition 23.4. tl0: timer 0 low byte bit 7 6 5 4 3 2 1 0 name tl0[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tl0[7:0] timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr definition 23.5. tl1: timer 1 low byte bit 7 6 5 4 3 2 1 0 name tl1[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tl1[7:0] timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1.
c8051f54x 236 rev. 1.1 sfr address = 0x8c; sfr page = all pages sfr address = 0x8d; sfr page = all pages sfr definition 23.6. th0: timer 0 high byte bit 7 6 5 4 3 2 1 0 name th0[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 th0[7:0] timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr definition 23.7. th1: timer 1 high byte bit 7 6 5 4 3 2 1 0 name th1[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 th1[7:0] timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1.
rev. 1.1 237 c8051f54x 23.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives the system clock while timer 2 (and/or the pca) is clocked by an external preci- sion oscillator. note that the external oscillator source divided by 8 is synchronized wi th the sys tem clock. 23.2.1. 16-bit time r with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded into the timer 2 register as shown in figure 23.4, and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generated on each timer 2 overflow. additionally , if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn.5) , an interrup t will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 23.4. timer 2 16-bit mode block diagram 23.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bi t timers (tmr2h and tmr2l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 23.5. tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external cloc k select bit (t2xclk in tmr2cn), as follows: external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
c8051f54x 238 rev. 1.1 the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled an d tf2len (tmr2cn.5) is set, an interrupt is gener- ated each time either tmr2l or tmr2h overflows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 23.5. timer 2 8-bit mode block diagram 23.2.3. external oscillator capture mode capture mode allows the external oscillato r to be measured aga inst the system clo ck. timer 2 can be clocked from the system clock, or the system clock divided by 12, depending on the t2ml (ckcon.4), and t2xclk bits. when a capture event is generat ed, the contents of timer 2 (tmr2h:tmr2l) are loaded into the timer 2 reload registers (tmr2rlh:t mr2rll) and the tf2h flag is set. a capture event is generated by the falling ed ge of the clock source bein g measured, which is the ex ternal oscilla tor / 8. by recording the difference between tw o successive timer capture values , the external os cillator frequency can be determined with respect to the timer 2 clock. the timer 2 clock should be much faster than the capture clock to achieve an accurate reading. timer 2 should be in 16-bit auto-reload mode when using capture mode. for example, if t2ml = 1b and tf2cen = 1b, timer 2 will clock every sysclk and capt ure every external clock divided by 8. if the sysclk is 24 mhz and the difference between two successive captures is 5984, then the external clock frequency is as follows: 24 mhz/(5984/8) = 0.032086 mhz or 32.086 khz t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk/12 0 0 sysclk/12 0 1 external clock/8 0 1 external clock/8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 1.1 239 c8051f54x this mode allows software to deter mine the external oscillator frequency when an rc network or capacitor is used to generate the clock source. figure 23.6. timer 2 external oscillator capture mode block diagram external clock / 8 sysclk / 12 sysclk 0 1 0 1 t2xclk ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2l tmr2h tclk tr2 tmr2rll tmr2rlh capture external clock / 8 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 tf2len tf2cen interrupt
c8051f54x 240 rev. 1.1 sfr address = 0xc8; bit-addressable; sfr page = 0x00 sfr definition 23.8. tmr2cn: timer 2 control bit 7 6 5 4 3 2 1 0 name tf2h tf2l tf2len tf2cen t2split tr2 t2xclk type r/w r/w r/w r/w r/w r/w r r/w reset 0 0 0 0 0 0 0 0 bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will oc cur when timer 2 overflows from 0xffff to 0x0000. when the timer 2 interrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte overflows regardless of the timer 2 mode. this bit is not automatically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 low byte interrupts. if timer 2 interrupts are also enabled, an interrupt will be ge nerated when the lo w byte of timer 2 overflows. 4 tf2cen timer 2 capture mode enable. 0: timer 2 capture mode is disabled. 1: timer 2 capture mode is enabled. 3 t2split timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. 2 tr2 timer 2 run control. timer 2 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is alwa ys enabled in split mode. 1 unused read = 0b; write = don?t care 0 t2xclk timer 2 external clock select. this bit selects the external clock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock so urce for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock an d the system clock for either timer. 0: timer 2 clock is the system clock divided by 12. 1: timer 2 clock is the external clock divi ded by 8 (synchronized with sysclk).
rev. 1.1 241 c8051f54x sfr address = 0xca; sfr page = 0x00 sfr address = 0xcb; sfr page = 0x00 sfr definition 23.9. tmr2rll: timer 2 relo ad register low byte bit 7 6 5 4 3 2 1 0 name tmr2rll[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tmr2rll[7:0] timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr definition 23.10. tmr2rlh: timer 2 relo ad register high byte bit 7 6 5 4 3 2 1 0 name tmr2rlh[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tmr2rlh[7:0] timer 2 reload register high byte. tmr2rlh holds the high byte of the reload value for timer 2.
c8051f54x 242 rev. 1.1 sfr address = 0xcc; sfr page = 0x00 sfr address = 0xcd; sfr page = 0x00 sfr definition 23.11. tmr2l: timer 2 low byte bit 7 6 5 4 3 2 1 0 name tmr2l[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tmr2l[7:0] timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8- bit mode, tmr2l contains the 8-bit low byte timer value. sfr definition 23.12. tmr2h timer 2 high byte bit 7 6 5 4 3 2 1 0 name tmr2h[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tmr2h[7:0] timer 2 high byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8- bit mode, tmr2h contains the 8-bit high byte timer value.
rev. 1.1 243 c8051f54x 23.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr3cn.3) defines the timer 3 operation mode. timer 3 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives the system clock while timer 3 (and/or the pca) is clocked by an external preci- sion oscillator. note that the external oscillator source divided by 8 is synchronized wi th the sys tem clock. 23.3.1. 16-bit time r with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tmr3rll) is loaded into the timer 3 register as shown in figure 23.7, and the timer 3 high byte overflow flag (tmr3cn.7) is set. if timer 3 interrupts are enabled, an interrupt will be generated on each timer 3 overflow. additionally, if time r 3 interrupts are enabled and the tf3len bit is set (tmr3cn.5), an interrupt will be generated each time the lower 8 bits (tmr3l) overflow from 0xff to 0x00. figure 23.7. timer 3 16-bit mode block diagram 23.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 23.8. tmr3rll holds the reload value for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sysclk or the clock defined by the timer 3 external cloc k select bit (t3xclk in tmr3cn), as follows: external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split tf3cen tf3l tf3h t3xclk tr3 0 1 t3xclk interrupt tf3len to adc, smbus to smbus tl3 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
c8051f54x 244 rev. 1.1 the tf3h bit is set when tmr3h overflows from 0xff to 0x00; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over- flows. if timer 3 interrupts are enabled and tf3len (t mr3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 23.8. timer 3 8-bit mode block diagram 23.3.3. external oscillator capture mode capture mode allows the external oscillato r to be measured aga inst the system clo ck. timer 3 can be clocked from the system clock, or the system clock divided by 12, depending on the t3ml (ckcon.6), and t3xclk bits. when a capture event is generat ed, the contents of timer 3 (tmr3h:tmr3l) are loaded into the timer 3 reload registers (tmr3rlh:t mr3rll) and the tf3h flag is set. a capture event is generated by the falling edge of th e clock source being meas ured, which is the exte rnal oscillator/8. by recording the difference between tw o successive timer capture values , the external os cillator frequency can be determined with respect to the timer 3 clock. the timer 3 clock should be much faster than the capture clock to achieve an accurate reading. timer 3 should be in 16-bit auto-reload mode when using capture mode. if the sysclk is 24 mhz and the difference between tw o successive captures is 5861, then the external clock frequency is as follows: 24 mhz/(5861/8) = 0.032754 mhz or 32.754 khz this mode allows software to deter mine the external oscillator frequency when an rc network or capacitor is used to generate the clock source. t3mh t3xclk tmr3h clock source t3ml t3xclk tmr3l clock source 0 0 sysclk/12 0 0 sysclk/12 0 1 external clock/8 0 1 external clock/8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 t3xclk 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split tf3cen tf3len tf3l tf3h t3xclk tr3 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 1.1 245 c8051f54x figure 23.9. timer 3 external oscillator capture mode block diagram external clock / 8 sysclk / 12 sysclk 0 1 0 1 t3xclk ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3l tmr3h tclk tr3 tmr3rll tmr3rlh capture external clock / 8 tmr3cn t3split tf3cen tf3l tf3h t3xclk tr3 tf3len tf3cen interrupt
c8051f54x 246 rev. 1.1 sfr address = 0x91; sfr page = 0x00 sfr definition 23.13. tmr3cn: timer 3 control bit 7 6 5 4 3 2 1 0 name tf3h tf3l tf3len tf3cen t3split tr3 t3xclk type r/w r/w r/w r/w r/w r/w r r/w reset 0 0 0 0 0 0 0 0 bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will oc cur when timer 3 overflows from 0xffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the timer 3 low byte overflows from 0xff to 0x00. tf3l will be set when the low byte overflows regardless of the timer 3 mode. this bit is not automatically cleared by hardware. 5 tf3len timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 low byte interrupts. if timer 3 interrupts are also enabled, an interrupt will be ge nerated when the lo w byte of timer 3 overflows. 4 tf3cen timer 3 capture mode enable. 0: timer 3 capture mode is disabled. 1: timer 3 capture mode is enabled. 3 t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bit auto-reload timers. 2 tr3 timer 3 run control. timer 3 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is alwa ys enabled in split mode. 1 unused read = 0b; write = don?t care 0 t3xclk timer 3 external clock select. this bit selects the external clock source for timer 3. if timer 3 is in 8-bit mode, this bit selects the external oscillator clock so urce for both timer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock an d the system clock for either timer. 0: timer 3 clock is the system clock divided by 12. 1: timer 3 clock is the external clock divi ded by 8 (synchronized with sysclk).
rev. 1.1 247 c8051f54x sfr address = 0x92; sfr page = 0x00 sfr address = 0x93; sfr page = 0x00 sfr definition 23.14. tmr3rll: timer 3 relo ad register low byte bit 7 6 5 4 3 2 1 0 name tmr3rll[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tmr3rll[7:0] timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. sfr definition 23.15. tmr3rlh: timer 3 relo ad register high byte bit 7 6 5 4 3 2 1 0 name tmr3rlh[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tmr3rlh[7:0] timer 3 reload register high byte. tmr3rlh holds the high byte of the reload value for timer 3.
c8051f54x 248 rev. 1.1 sfr address = 0x94; sfr page = 0x00 sfr address = 0x95; sfr page = 0x00 sfr definition 23.16. tmr3l: timer 3 low byte bit 7 6 5 4 3 2 1 0 name tmr3l[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tmr3l[7:0] timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8- bit mode, tmr3l contains the 8-bit low byte timer value. sfr definition 23.17. tmr3h timer 3 high byte bit 7 6 5 4 3 2 1 0 name tmr3h[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 tmr3h[7:0] timer 3 high byte. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8- bit mode, tmr3h contains the 8-bit high byte timer value.
rev. 1.1 249 c8051f54x 24. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. each capt ure/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the counter/timer is driven by a programmable timebase that can select between six sour ces: system clock, system clock divided by four, system clock divided by twelve , the external oscillator clock source di vided by 8, timer 0 overflows, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre- quency output, 8 to 11-bit pwm, or 16-bit pwm (each mode is described in section ?24.3. capture/compare modules? on page 252). the external oscillator clock option is ideal for real-time clock (rtc) functionality, allowing the pca to be cloc ked by a precision external oscillator while the inter- nal oscillator drives the system clo ck. the pca is configured and cont rolled through the system controller's special function registers. the pca bl ock diagram is shown in figure 24.1 important note: the pca module 5 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 24.4 for details. figure 24.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 4 capture/compare module 3 capture/compare module 5 / wdt cex4 cex5 cex3
c8051f54x 250 rev. 1.1 24.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the low byte (lsb). reading pca0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps[2:0] bits in the pca0md reg- ister select the timebase for the counter/timer as shown in table 24.1. when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the inte rrupt service routine, and must be cleared by soft- ware. clearing the cidl bit in the pca0md register a llows the pca to continue normal operation while the cpu is in idle mode. table 24.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12. 0 0 1 system clock divided by 4. 0 1 0 timer 0 overflow. 0 1 1 high-to-low transitions on eci (max rate = system clock divided by 4). 1 0 0 system clock. 1 0 1 external oscillator source divided by 8. * 1 1 x reserved. *note: external oscillator source divided by 8 is synchronized with the system clock.
rev. 1.1 251 c8051f54x figure 24.2. pca counter/timer block diagram 24.2. pca0 interrupt sources figure 24.3 shows a diagram of the pca interrupt tree. there are five independent event flags that can be used to generate a pca0 interrupt. they are as follo ws: the main pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter, an in termediate overflow flag (covf), which can be set on an overflow from the 8th, 9th, 10th, or 11th bit of the pca0 counter, and the individual flags for each pca channel (ccf0, ccf1, ccf2, ccf3, ccf4, and ccf5), which are set according to the operation mode of that module. these event flags are always set when the trigger condition occurs. each of these flags can be individually selected to genera te a pca0 interrupt, using the corresponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pc a0 interrupts must be globally enabled before any individual interrupt sources are recognized by the pr ocessor. pca0 interrupts are globally enabled by set- ting the ea bit and the epca0 bit to logic 1. pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 c c f 3 c c f 5 c c f 4
c8051f54x 252 rev. 1.1 figure 24.3. pca interrupt block diagram 24.3. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16- bit pulse width modulator. each module has special func tion registers (sfrs) associated with it in the cip-51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. table 24.2 summariz es the bit settings in the pca0cpmn and pca0pwm registers used to select the pca capture/compare modu le?s operating mode. all modules set to use 8, 9, 10, or 11-bit pwm mode must use the same cycle length (8-11 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/timer 16- bit overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 2) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0pwm a r s e l c o v f c l s e l 0 c l s e l 1 e c o v pca counter/timer 8, 9, 10 or 11-bit overflow 0 1 set 8, 9, 10, or 11 bit operation pca module 3 (ccf3) pca module 4 (ccf4) pca module 5 (ccf5) c c f 3 c c f 5 c c f 4 eccf3 eccf4 eccf5 0 1 0 1 0 1
rev. 1.1 253 c8051f54x 24.3.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture the value of the pca coun- ter/timer and load it into the corresponding module 's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an in terrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. if both cappn and capnn bits are set to l ogic 1, then the state of the port pin associated with cexn can be r ead directly to determine whether a rising-edge or fall- ing-edge caused the capture. table 24.2. pca0cpm and pca0pwm bit settings for pca capture/compare modules operational mode pca0cpmn pca0pwm bit number 7 6 5 4 3 2 1 0 7 6 5 4?2 1?0 capture triggered by positive edge on cexn x x 1 0 0 0 0 a 0 x b xxx xx capture triggered by negative edge on cexn x x 0 1 0 0 0 a 0 x b xxx xx capture triggered by any transition on cexn x x 1 1 0 0 0 a 0 x b xxx xx software timer x c 0 0 1 0 0 a 0 x b xxx xx high speed output x c 0 0 1 1 0 a 0 x b xxx xx frequency output x c 0 0 0 1 1 a 0 x b xxx xx 8-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a 0 x b xxx 00 9-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a d x b xxx 01 10-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a d x b xxx 10 11-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a d x b xxx 11 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b xxx xx notes: 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = 1 to enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = 1 to enable 8th, 9th, 10th or 11th bit overflow interrupt (depends on setting of clsel[1:0]). 4. c = when set to 0, the digital comparator is off. for high speed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, this gener ates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pca0cphn and pca0cpln. 6. e = when set to 1, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8, 9, 10 or 11-bit pwm mode use the same cycle length setting.
c8051f54x 254 rev. 1.1 figure 24.4. pca capture mode diagram note: the cexn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware. 24.3.2. software timer (compare) mode in software timer mode, the pca counter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn regis- ter enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt x000x x c c f 3 c c f 5 c c f 4
rev. 1.1 255 c8051f54x figure 24.5. pca software timer mode diagram 24.3.3. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if th e ccfn interrupt for that module is enabled. the ccfn bit is not auto- matically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bi ts in the pca0cpmn register enables the high- speed output mode. if ecomn is cleare d, the associated pin will retain it s state, and not toggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt c c f 0 c c f 2 c c f 1
c8051f54x 256 rev. 1.1 figure 24.6. pca high-speed output mode diagram 24.3.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out- put is toggled. the frequency of the square wave is then defined by equation 24.1. equation 24.1. square wave frequency output where f pca is the frequency of the clock selected by the cps[2 : 0] bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg- ister. note that the matn bit should normally be set to 0 in this mode. if the matn bit is set to 1, the ccfn flag for the channel will be set when the 16-bit pca0 co unter and the 16-bit capture/comp are register for the channel are equal. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt c c f 3 c c f 5 c c f 4 f cexn f pca 2 pca 0 cphn ? ---------------------- -------------------- - = note: a value of 0x00 in the pca0cphn re gister is equal to 256 for this equation.
rev. 1.1 257 c8051f54x figure 24.7. pca frequency output mode 24.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modulator modes each module can be used independently to generate a pulse width modulated (pwm) output on its associ- ated cexn pin. the frequency of the output is depe ndent on the timebase for the pca counter/timer, and the setting of the pwm cycle length (8, 9, 10 or 11-bits). for backwar ds-compatibility wi th the 8-bit pwm mode available on other devices, the 8-bit pwm mode operates slightly differen t than 9, 10 and 11-bit pwm modes. it is important to note that all channels configured for 8/9/10/11-bit pwm mode will use the same cycle length. it is not possible to configure one channel for 8-bit pwm mode and another for 11- bit mode (for example). however, other pca channels can be configured to pin capture, high-speed out- put, software timer, frequency output, or 16-bit pwm mode independently. 24.3.5.1. 8-bit puls e width modulator mode the duty cycle of the pwm output signal in 8-bit pwm mode is varied using the module's pca0cpln cap- ture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on th e cexn pin will be set. when the co unt value in pca 0l overflows, the cexn output will be reset (see figu re 24.8). also, when th e counter/timer lo w byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulator mode. if the matn bit is se t to 1, the ccfn flag for the modu le will be set each time an 8-bit comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 256 pca clock cyc les. the duty cycle for 8-bit pwm mode is given in equation 24.2. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 24.2. 8-bit pwm duty cycle using equation 24.2, the largest duty cycle is 100 % (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset duty cycle 256 pca0cphn ? ?? 256 ------------------------------------------------------ - =
c8051f54x 258 rev. 1.1 figure 24.8. pca 8-bit pwm mode diagram 24.3.5.2. 9/10/1 1-bit pulse width modulator mode the duty cycle of the pwm output signa l in 9/10/11-bit pwm mode should be varied by writing to an ?auto- reload? register, which is dual-mapped into the pc a0cphn and pca0cpln register locations. the data written to define the duty cycle should be right-just ified in the registers. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to 1. the capture/compare registers are accessed when arsel is set to 0. when the least-significant n bits of the pca0 coun ter match the value in the associated module?s cap- ture/compare register (pca0cpn), the output on cexn is asserted high. when the counter overflows from the nth bit, cexn is asserted low (see figure 24.9). up on an overflow from the nth bit, the covf flag is set, and the value stored in the module?s auto-reload r egister is loaded into the capture/compare register. the value of n is determined by the clsel bits in register pca0pwm. the 9, 10 or 11-bit pwm mode is selected by setting the ecomn and pwmn bits in the pca0cpmn regis- ter, and setting the clsel bits in register pca0pwm to the desired cycle length (other than 8-bits). if the matn bit is set to 1, the ccfn flag for the module will be set each ti me a comparator ma tch (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) pca clock cycles . the duty cycle for 9/10/11-bit pwm mode is given in equation 24.2, where n is the number of bits in the pwm cycle. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be wr itten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 24.3. 9, 10, and 11-bit pwm duty cycle a 0% duty cycle may be generated by clearing the ecomn bit to 0. 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c o v f c l s e l 0 c l s e l 1 e c o v x0 0 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset covf duty cycle 2 n pca0cpn ? ?? 2 n ----------------------------------------------- - =
rev. 1.1 259 c8051f54x figure 24.9. pca 9, 10 and 11-bit pwm mode diagram 24.3.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. 16-bit pwm mode is independent of the other (8/9/10/11-bit) pwm modes. in this mode, the 16-bit capture/compare module defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the out- put on cexn is asserted high; when the 16-bit counter overflows, cexn is asserted low. to output a vary- ing duty cycle, new value writes should be synchronized with pca ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pw m16n bits in the pca0cpmn register. for a vary- ing duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/comp are register writes. if the matn bit is set to 1, the ccfn flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. the cf flag in pca0cn can be used to detect the overflow (falling edge). the du ty cycle for 16-bit pwm mode is given by equation 24.4. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 24.4. 16-bit pwm duty cycle using equation 24.4, the largest duty cycle is 100% (pca0cpn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. n-bit comparator pca0h:l (capture/compare) pca0cph:ln (right-justified) (auto-reload) pca0cph:ln (right-justified) cexn crossbar port i/o enable overflow of n th bit pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c o v f c l s e l 0 c l s e l 1 e c o v x enb enb 0 1 write to pca0cpln write to pca0cphn reset r/w when arsel = 1 r/w when arsel = 0 set ?n? bits: 01 = 9 bits 10 = 10 bits 11 = 11 bits duty cycle 65536 pca0cpn ? ?? 65536 -------------------------------------------------------- - =
c8051f54x 260 rev. 1.1 figure 24.10. pca 16-bit pwm mode 24.4. watchdog timer mode a programmable watchdog timer (wdt) function is avai lable through the pca module 5. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph5) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, modu le 5 operates as a watchdog timer (wdt). the mod- ule 5 high byte is compared to the pca counter high byte; the module 5 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. the wdt will generate a reset shortly after code begins execution. to avoid this re set, the wdt should be explicitly disabled (and option- ally re-configured and re-enabled if it is used in the system). 24.4.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps[2:0]) are frozen. ? pca idle control bit (cidl) is frozen. ? module 5 is forced into software timer mode. ? writes to the module 5 mode register (pca0cpm5) are disabled. while the wdt is enabled, wr ites to the cr bit will not change the pca c ounter state; the counter will run until the wdt is disabled. the pca counter run co ntrol bit (cr) will read zero if the wdt is enabled but user software has not enabled th e pca counter. if a match occurs between pca0cph5 and pca0h while the wdt is enabled, a reset will be generated. to pr event a wdt reset, the wd t may be updated with a write of any value to pca0cph5. upon a pca0cph5 write, pca0h plus the offset held in pca0cpl5 is loaded into pca0cph5 (see figure 24.11). pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset
rev. 1.1 261 c8051f54x figure 24.11. pca module 2 with watchdog timer enabled note that the 8-bit offset held in pca0cph5 is comp ared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the valu e of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 24.5, where pca0l is the value of the pca0l register at the time of the update. equation 24.5. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph5 and pca0h. software may force a wdt reset by writing a 1 to the ccf5 flag (pca0cn.5) while the wdt is enabled. 24.4.2. watchdog timer usage to configure the wdt, perform the following tasks: ? disable the wdt by writing a 0 to the wdte bit. ? select the desired pca clock s ource (with the cps[2:0] bits). ? load pca0cpl5 with the desi red wdt update offset value. ? configure the pca idle mode (set cidl if the wd t should be suspended while the cpu is in idle mode). ? enable the wdt by setting the wdte bit to 1. ? reset the wdt timer by writing to pca0cph5. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any reset. the pca0 c ounter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl5 defaults to 0x00. using equation 24.5, this results in a wdt timeout interval of 256 pca clock cycles, or 3072 syste m clock cycles. table 24.3 lists some example time- out intervals for typical system clocks. pca0h enable pca0l overflow reset pca0cpl5 8-bit adder pca0cph5 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph2 8-bit comparator offset 256 x pca0cpl5 ?? 256 pca0l ? ?? + =
c8051f54x 262 rev. 1.1 table 24.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl5 timeout interval (ms) 24,000,000 255 32.8 24,000,000 128 16.5 24,000,000 32 4.2 3,000,000 255 262.1 3,000,000 128 132.1 3,000,000 32 33.8 187,500 2 255 4194 187,500 2 128 2114 187,500 2 32 541 notes: 1. assumes sysclk/12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. internal sysclk reset frequency = internal oscillator divided by 128.
rev. 1.1 263 c8051f54x 24.5. register d escriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of the pca. sfr address = 0xd8; bit-addressable; sfr page = 0x00 sfr definition 24.1. pca0cn: pca control bit 7 6 5 4 3 2 1 0 name cf cr ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cf pca counter/timer overflow flag. set by hardware when the pca counter/ timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service r outine. this bit is not automatically cleared by hardware and must be cleared by software. 6 cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5 ccf5 pca module 5 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf5 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou - tine. this bit is not automatically cleared by hardware and must be cleared by software. 4 ccf4 pca module 4 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf4 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou - tine. this bit is not automatically cleared by hardware and must be cleared by software. 3 ccf3 pca module 3 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf3 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou - tine. this bit is not automatically cleared by hardware and must be cleared by software. 2 ccf2 pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf2 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou - tine. this bit is not automatically cleared by hardware and must be cleared by software. 1 ccf1 pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf1 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou - tine. this bit is not automatically cleared by hardware and must be cleared by software. 0 ccf0 pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf0 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou - tine. this bit is not automatically cleared by hardware and must be cleared by software.
c8051f54x 264 rev. 1.1 sfr address = 0xd9; sfr page = 0x00 sfr definition 24.2. pca0md: pca mode bit 7 6 5 4 3 2 1 0 name cidl wdte wdlck cps[2:0] ecf type r/w r/w r/w r r/w r/w r/w r/w reset 0 1 0 0 0 0 0 0 bit name function 7 cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system co ntroller is in idle mode. 1: pca operation is suspended while th e system controller is in idle mode. 6 wdte watchdog timer enable if this bit is set, pca module 5 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 5 enabled as watchdog timer. 5 wdlck watchdog timer lock this bit locks/unlocks the watchdog timer enable. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. 4 unused read = 0b, write = don't care. 3:1 cps[2:0] pca counter/timer pulse select. these bits select the timebase source for the pca counter 000: system clock divided by 12 001: system clock divided by 4 010: timer 0 overflow 011: high-to-low transitions on eci (max rate = system clock divided by 4) 100: system clock 101: external clock divided by 8 (synchronized with the system clock) 11x: reserved 0 ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow in terrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to 1, the other bits in the pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled.
rev. 1.1 265 c8051f54x sfr address = 0xd9; sfr page = 0x0f sfr definition 24.3. pca0pwm: pca pwm configuration bit 7 6 5 4 3 2 1 0 name arsel ecov covf clsel[1:0] type r/w r/w r/w r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7 arsel auto-reload register select. this bit selects whether to read and write the normal pca capture/compare registers (pca0cpn), or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9, 10, and 11-bit pwm modes. in all other modes, the auto-reload registers have no function. 0: read/write capture/compare registers at pca0cphn and pca0cpln. 1: read/write auto-reload regi sters at pca0cphn and pca0cpln. 6 ecov cycle overflow interrupt enable. this bit sets the masking of the cycle overflow flag (covf) interrupt. 0: covf will not gene rate pca interrupts. 1: a pca interrupt will be ge nerated when covf is set. 5 covf cycle overflow flag. this bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main pca counter (pca0). the specific bit used for this flag depends on the setting of the cycle length select bits. the bit can be set by hardware or software, but must be cleared by soft - ware. 0: no overflow has occurred since the last time this bit was cleared. 1: an overflow has occurred since the last time this bit was cleared. 4:2 unused read = 000b; write = don?t care. 1:0 clsel[1:0] cycle length select. when 16-bit pwm mode is not selected, th ese bits select the length of the pwm cycle, between 8, 9, 10, or 11 bits. this affects all channels configured for pwm which are not using 16-bit pwm mode. these bits are ignored for individual channels config - ured to16-bit pwm mode. 00: 8 bits. 01: 9 bits. 10: 10 bits. 11: 11 bits.
c8051f54x 266 rev. 1.1 sfr addresses: pca0cpm0 = 0xda , pca0cpm1 = 0xdb , pca0cpm2 = 0xdc; pca0cpm3 = 0xdd, pca0cpm4 = 0xde, pca0cpm5 = 0xdf, sfr page (all registers) = 0x00 sfr definition 24.4. pca0cpmn: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16n ecomn cappn capnn matn togn pwmn eccfn type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 pwm16n 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecomn comparator function enable. this bit enables the comparator function for pca module n when set to 1. 5 cappn capture positive function enable. this bit enables the positive edge capture for pca module n when set to 1. 4 capnn capture negative function enable. this bit enables the negative edge capture for pca module n when set to 1. 3 matn match function enable. this bit enables the match function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare register cause the ccfn bit in pca0md register to be set to logic 1. 2 togn toggle function enable. this bit enables the toggle function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle . if the pwmn bit is also set to logic 1, the module oper - ates in frequency output mode. 1 pwmn pulse width modulation mode enable. this bit enables the pwm function for pca module n when set to 1. when enabled, a pulse width modulated signal is output on the cexn pin. 8 to 11-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm1 6n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0 eccfn capture/compare flag interrupt enable. this bit sets the masking of the ca pture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. note: when the wdte bit is set to 1, the pca0cpm5 regi ster cannot be modified, and module 5 acts as the watchdog timer. to change the contents of the pca0cpm5 register or the function of module 5, the watchdog timer must be disabled.
rev. 1.1 267 c8051f54x sfr address = 0xf9; sfr page = 0x00 sfr address = 0xfa; sfr page = 0x00 sfr definition 24.5. pca0l: pca counter/timer low byte bit 7 6 5 4 3 2 1 0 name pca0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0[7:0] pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. note: when the wdte bit is set to 1, the pca0l register cannot be modified by software. to change the contents of the pca0l register, the watchdog timer must first be disabled. sfr definition 24.6. pca0h: pca counter/timer high byte bit 7 6 5 4 3 2 1 0 name pca0[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0[15:8] pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. reads of this register will read the contents of a ?snapsh ot? register, whose contents are updated only when the cont ents of pca0l are read (see section 24.1 ). note: when the wdte bit is set to 1, the pca0h register cannot be modified by software. to change the contents of the pca0h register, the watchdog timer must first be disabled.
c8051f54x 268 rev. 1.1 sfr addresses: pca0cpl0 = 0xfb , pca0cpl1 = 0xe9 , pca0cpl2 = 0xeb, pca0cpl3 = 0xed , pca0cpl4 = 0xfd , pca0cpl5 = 0xce; sfr pa ge (all registers) = 0x00 sfr addresses: pca0cph0 = 0xfc , pca0cph1 = 0xea , pca0cph2 = 0xec, pca0cph3 = 0xee , pca0cph4 = 0xfe , pca0cph5 = 0xcf; sfr page (all registers) = 0x00 sfr definition 24.7. pca0cpln: pca capt ure module low byte bit 7 6 5 4 3 2 1 0 name pca0cpn[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0cpn[7:0] pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. this register address also allows acce ss to the low byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will clear the module?s ecomn bit to a 0. sfr definition 24.8. pca0cphn: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cpn[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0cpn[15:8] pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. this register address also allows access to the high byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will set the module?s ecomn bit to a 1.
rev. 1.1 269 c8051f54x 25. c2 interface c8051f54x devices incl ude an on-chip silicon labs 2-wire (c2) debug interface to allow flash program- ming and in-system debugging with the production part installed in the end application. the c2 interface uses a clock signal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a host system. see the c2 interface specification for details on the c2 protocol. 25.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming through the c2 inter- face. all c2 registers are accessed through the c2 inte rface as described in the c2 interface specification. c2 register definition 25.1. c2add: c2 address bit 7 6 5 4 3 2 1 0 name c2add[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 c2add[7:0] c2 address. the c2add register is accessed via the c2 interface to select the target data register for c2 data read and data write commands. address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id register for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xb4 selects the c2 flash programming data register for data read/write instructions
c8051f54x 270 rev. 1.1 c2 address = 0xfd ; sfr address = 0xfd; sfr page = 0xf c2 address = 0xfe ; sfr address = 0x fe; sfr page = 0xf c2 register definition 25.2. deviceid: c2 device id bit 7 6 5 4 3 2 1 0 name deviceid[7:0] type r/w reset 0 0 0 1 0 1 0 0 bit name function 7:0 deviceid[7:0] device id. this read-only register returns the 8-bit device id: 0x22 (c8051f54x). c2 register definition 25.3. revid: c2 revision id bit 7 6 5 4 3 2 1 0 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 7:0 revid[7:0] revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a.
rev. 1.1 271 c8051f54x c2 address: 0x02 c2 address: 0xb4 c2 register definition 25.4. fpctl: c2 flash programming control bit 7 6 5 4 3 2 1 0 name fpctl[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 fpctl[7:0] flash programming control register. this register is used to enable flash programming via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is ena bled, a system reset must be issued to resume normal operation. c2 register definition 25.5. fpdat: c2 flash programming data bit 7 6 5 4 3 2 1 0 name fpdat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 fpdat[7:0] c2 flash programming data register. this register is used to pass flash commands, addresses, and data during c2 flash accesses. valid commands are listed below. code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
c8051f54x 272 rev. 1.1 25.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface c an safely ?borrow? the c2ck (rst ) and c2d pins. in most applications, external resistors are required to isolate c2 interface traffic from the user application. a typical isolation configuration is shown in figure 25.1. figure 25.1. typical c2 pin sharing the configuration in figure 25.1 assumes the following: 1. the user input (b) cannot change state while the target device is halted. 2. the rst pin on the target device is used as an input only. ? additional resistors may be necessary depending on the specific application. c2d c2ck rst (a) input (b) output (c) c2 interface master c8051fxxx
rev. 1.1 273 c8051f54x d ocument c hange l ist revision 0.1 to revision 1.0 ? updated ?2. ordering information? to include -a (automotive) devices and automotive qualification information. ? updated figure 4.6 . ? updated supply current related specifications throughout ?6. electrical characteristics? . ? updated sfr definition 7.1 (ref0cn) to change vref high setting to 2.20 v from 2.25 v. ? updated figure 8.1 to indicate that comparators are powered from v io and not v dda . ? updated the gain table in ?5.3.1. calculating the gain value? to fix the adc0gnh value in the last row. ? updated ta b l e 10.1 with correct timing for all bran ch instructions, movc, and cpl a. ? updated ta b l e 14.1 to indicate behavior when performing a flash operation in reserved space. ? updated ?14.1. programming the flash memory? to clarify behavior of 8-bit movx instructions and when writing/erasing flash. ? updated sfr definition 14.3 (flscl) to include flewt bit definit ion. this bit must be set before writing or erasing flash. also updated ta b l e 6.5 to reflect new flash write and erase timing. ? updated ?16.7. flash error reset? with an additional cause of a flash error reset. ? updated ?18.1.3. interfacing port i/o in a multi-voltage system? to remove note rega rding interfacing to voltages above vio. ? updated ?20. smbus? to remove all hardware ack features, including smb0adm and smb0adr sfrs. ? updated sfr definition 21.1 (scon0) to correct sfr page to 0x00 from all pages. ? updated cp register definition 24.2 with proper device id. note: all items from the c8051f54x errata dated november 5th, 2009 are incorporated into this data sheet. revision 1.0 to revision 1.1 ? updated ?1. system overview? with a voltage range specificat ion for the internal oscillator. ? updated figure 5.4, ?12-bit adc burst mode example with repeat count set to 4,? on page 33 with new timing diagram when using cnvstr pin. ? updated ta b l e 6.6, ?internal high-frequen cy oscillator electrical characteristics,? on page 53 with new conditions for the intern al oscillator accuracy. the internal o scillator accuracy is dependent on the operating voltage range. ? updated ?6. electrical characteristics? to remove the internal oscilla tor curve across temperature diagram. ? updated sfr definition 7.1 (ref0cn) with oscillator su spend requirem ent for ztcen. ? fixed incorrect cro ss references in ?8. comparators? . ? updated sfr definition 9.1 (reg0cn) with a new definition for bit 6. the bit 6 reset value is 1b and must be written to 1b. ? updated figure 11.2, ?flash program memory map,? on page 86 with correct address for start of lock byte page from 0x3900 to 0x3a00. ? updated ?15.3. suspend mode? with note regarding ztcen. ? added port 2 event and port 3 event to wake-up sources in ?17.2.1. internal o scillator susp end mode? ? updated ?19. local interconnect network (lin)? with a voltage range specification for the internal oscillator. ? updated lin register definitions for lin0mu l and lin0div to correct the reset value. ? updated c2 register definitions 25.2 and 25.3 with correct c2 and sfr addresses.
c8051f54x 274 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 w. cesar chavez ? austin, tx 78701 ? tel: 1+(512) 416-8500 ? fax: 1+(512) 416-9669 ? toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders. the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laborator ies assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories re serves the right to make change s without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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